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handling reset during transition fault pattern generation

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anjana_das

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hi,

While generating patterns for transition faults, should the reset be declared as a clock or not?

How does declaring the reset as clock help in increasing test coverage for transition patterns when it is known that the reset cannot toggle at speed? Will such patterns pass in the tester?

Regards
Anjana
 

Re: handling reset during transition fault pattern generatio

You can just add pin constraints on the reset signal. that is set the pin to the constant value and it will not toggle in the at speed test.
 

Re: handling reset during transition fault pattern generatio

While doing Transition testing even if you define the reset as a clock it will not harm anyway.

None of the clocks fault are added in the transition fault model and even if the reset is defined as a clock you can constrain the same to its off state during ATPG.

And in Tetramax if you dont constrain your asynchronus signals then you get a warning at the starting of the ATPG (M487)
 

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