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  1. #1
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    vhdl code for sr flip flop

    Hello,

    i am trying to build VGA controller. it will have 2 10 bit up counters and 4 flip flops. i already have a schematic of it.

    now i want to write down complete VHDL structural code for my SR flip flop, please take a look at the image of the flip flop which i need inside my controller.

    as i see from the Enoch's book, SR flip flop is just modified D flip flop, please take a look at the second pic.

    now, i need to modify VHDL code for SR flip flop, but i also need to include asynchronous clear signal, as shown on the first pic,...for the VGA controller..

    here is my code:

    Code:
    -- define the operation of the 2-input NAND gate
    LIBRARY IEEE;
    USE IEEE.STD_LOGIC_1164.ALL;
    ENTITY NAND_2 IS PORT (
    I0, I1: IN STD_LOGIC;
    O: OUT STD_LOGIC);
    END NAND_2;
    ARCHITECTURE Dataflow_NAND2 OF NAND_2 IS
    BEGIN
    O <= I0 NAND I1;
    END Dataflow_NAND2;
    
    -- define the operation of the 3-input NAND gate
    LIBRARY IEEE;
    USE IEEE.STD_LOGIC_1164.ALL;
    
    ENTITY NAND_3 IS PORT (
    I0, I1, I2: IN STD_LOGIC;
    O: OUT STD_LOGIC);
    END NAND_3;
    ARCHITECTURE Dataflow_NAND3 OF NAND_3 IS
    BEGIN
    O <= NOT (I0 AND I1 AND I2);
    END Dataflow_NAND3;
    
    
    -- define the operation of the SR input block to the D flip-flop
    LIBRARY IEEE;
    USE IEEE.STD_LOGIC_1164.ALL;
    ENTITY SRin IS PORT (
    R, S, Q: IN STD_LOGIC;
    D: OUT STD_LOGIC);
    END SRin;
    ARCHITECTURE Dataflow_SRin OF SRin IS
    BEGIN
    D <= (Q AND (NOT R)) OR S ;
    END Dataflow_SRin;
    
    
    
    -- define the structural operation of the SR latch
    LIBRARY IEEE;
    USE IEEE.STD_LOGIC_1164.ALL;
    
    ENTITY SRlatch IS PORT (
    SN, RN: IN STD_LOGIC;
    Q, QN: BUFFER STD_LOGIC);
    END SRlatch;
    
    
    ARCHITECTURE Structural_SRlatch OF SRlatch IS
    COMPONENT NAND_2 PORT (
    I0, I1 : IN STD_LOGIC;
    O : OUT STD_LOGIC);
    END COMPONENT;
    
    BEGIN
    U1: NAND_2 PORT MAP (SN, QN, Q);
    U2: NAND_2 PORT MAP (Q, RN, QN);
    END Structural_SRlatch;
    
    
    -- define the structural operation of the SR flip-flop
    LIBRARY IEEE;
    USE IEEE.STD_LOGIC_1164.ALL;
    
    ENTITY SR-FF IS PORT (
    S, R, Clear, Clock: IN STD_LOGIC;
    Q : BUFFER STD_LOGIC);
    END SR-FF;
    
    ARCHITECTURE Structural_SR-FF OF SR-FF IS
    SIGNAL N1, N2, N3, N4, N5: STD_LOGIC;
    
    COMPONENT SRlatch PORT (
    SN, RN: IN STD_LOGIC;
    Q, QN: BUFFER STD_LOGIC);
    END COMPONENT;
    
    COMPONENT NAND_2 PORT (
    I0, I1: IN STD_LOGIC;
    O: OUT STD_LOGIC);
    END COMPONENT;
    
    COMPONENT NAND_3 PORT (
    I0, I1, I2: IN STD_LOGIC;
    O: OUT STD_LOGIC);
    END COMPONENT;
    
    COMPONENT SRin PORT (
        S, R, Q: IN STD_LOGIC;
        D: OUT STD_LOGIC);
    END COMPONENT
    
    BEGIN
    U1: SRlatch PORT MAP (N4, Clock, N1, N2, Clear); -- set latch
    U2: SRlatch PORT MAP (N2, N3, Q, QN, Clear); -- output latch
    U3: NAND_3 PORT MAP (N2, Clock, N4, N3); -- reset latch
    U4: NAND_2 PORT MAP (N3, N5, N4, Clear); -- reset latch
    U5: SRin PORT MAP (S, R, Q, N5); -- SR INPUT
    END StructuralDFF;
    i compiled it in Modelsim, it gave me errors, but i dont understand them good...can u take a look and say what could be wrong?

    can u say me is it normally designed SR flip flop model?

    and one more thing... in my VGA controller from the Enoch's book, i will have 4 of such flip flops... do i have to write them all down in structural code in one source VHD file??? or can i write down one structural code for this flip flop and use it in my main controller source file? if yes then how?


    can i write down just behavioral code for this flip flop? will it work if i will want to create this controller on XUPV2P virtex2 board? or i need only structural?

    (anyway i think structural is more complete)
    [/code]

  2. #2
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    sr flip flop vhdl

    S R and CLK?

    library IEEE;
    use IEEE.STD_LOGIC_1164.all;

    entity FDRS is

    port(
    Q : out std_ulogic;

    C : in std_ulogic;
    R : in std_ulogic;
    S : in std_ulogic;
    Clear: in std_ulogic
    );
    end FDRS;

    architecture FDRS_arch of FDRS is
    begin
    process(C,Clear)
    begin
    if (rising edge(Clear)) then
    Q <= '0';
    end if;
    if (rising_edge(C)) then
    if (Clear = '1')
    Q <=0;
    elsif (R = '1') then
    Q <= '0' ;
    elsif (S = '1') then
    Q <= '1' ;
    end if;
    end if;
    end process;
    end FDRS_arch;


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  3. #3
    FvM
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    sr flip flop vhdl code

    To my opinion, you "invented" a new kind of SR-Flipflop - with a clock. I never saw it before.



    •   Alt29th February 2008, 19:03

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  4. #4
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    vhdl code for jk flip flop

    i did not invent anything! havent u read a book of Enoch Hwang? those pictures on my post are from that book! so?.... any ideas? and what do u think about that VHDL code?



  5. #5
    FvM
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    sr latch vhdl

    Hello,

    O.K., I see that SR-Flipflop is used by Enoch and elsewhere. I found however, that different implementations exist that differ regarding the behaviour with R and S both H. Enoch says "SR flip-flops can enter an undefined state when both inputs are asserted simultaneously". In constrast his presented circuit has well defined behaviour achieving priority for S input. Altera MaxPlus has SR-Flipflop that's toggling with S and R both H and the code posted by mstrcosmos has priority for R input.

    Apart from this particular problem, the VHDL code seems correct. Instead of using "structural" code that has partial unclear behaviour, I would prefer a clear description. The required priority for SR flipflop can be actually different. Using D-flipflops you have to define the intended logic explicitely.

    The SR-flipflop description by mstrcosmos isn't synthesizable this way, cause it has two edge sensitive signals. The usual construct with asynchronouos clear should be used instead. As already said, it differs from your code regarding R versus S priority.
    Code:
    process(C,Clear) 
    begin 
    if (Clear) then 
    Q <= '0'; 
    elsif (rising_edge(C)) then 
    if (R = '1') then 
    Q <= '0' ; 
    elsif (S = '1') then 
    Q <= '1' ; 
    end if; 
    end if; 
    end process;
    Regards,
    Frank


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    •   Alt29th February 2008, 23:18

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  6. #6
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    vhdl flip flops

    u have provided behavioral code... can i use it to build VGA controller for my Virtex2 pro chip, with ISE? and can i place it in another.. "header" file.. so that i wont use it in main controller source code?



    •   Alt1st March 2008, 04:52

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    vhdl code for t flip flop

    Yes.you can use it.



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    set reset flip flop vhdl

    But is it meaningful?



  9. #9
    FvM
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    structural vhdl code

    I reviewed the original "structural" code. It's absolutely unsuitable for synthesis (if correct so far, which I didn't check completely). Synthesizable code (as far as clock synchronouos action is intended) must be based on D-FF logic elements respectively clock synchronous HDL constructs.

    P.S.: I assumed your code is intended for synthesis in hardware, but you didn't mention it. I understand now, that you coded the structural D-FF view from Enochs book. The view basically gives an idea, how a D-FF could operate in hardware, but it's neither meaningful for synthesis nor simulation to my opinion.

    A synthesis tool, that usually operates on a higher abstraction level than individual gates, most likely wouldn't recognize it in a way that utilizes a D-FF at gate level. A simulation tool should basically reproduce the behaviour, but would also cause much overhead compared to a higher level description (behavioral or using hardware D-FF).

    Behavioral descriptions has two limitations: Some constructs aren't synthesizable, e. g. delay statement and it may not give optimal results in all cases, where particular logic hardware resources are available. But to improve performance with structural code, it must consider the particular logic hardware, usually through vendor libraries.



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    verilog code for jk flip flop

    thank u! ok i have coded it like you showed me, here is the behavioral code:

    Code:
    LIBRARY IEEE;
    USE IEEE.STD_LOGIC_1164.ALL;
    
    ENTITY SRff IS PORT (
    S, R, Clock, Clear: IN STD_LOGIC;
    Q: OUT STD_LOGIC);
    END SRff;
    
    ARCHITECTURE Behavior OF SRff IS
    BEGIN
    PROCESS(Clock, Clear) -- sensitivity list is used
    BEGIN
        IF (Clear = '1') THEN
            Q <=  '0';    
    ELSE
    
    IF Clock'EVENT AND Clock = '1' THEN
        IF (R = '1') THEN
            Q <= '0';
            ELSIF (S = '1') THEN
                Q <= '1';
            END IF;
        END IF;
    END IF;
    
    END PROCESS;
    END Behavior;
    it compiled without errors, now u think i can use this piece of code to implement VGA controller from Enochs book? (on my Virtex2 pro board) ?

    thanks



  11. #11
    FvM
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    vhdl code for t flip-flop

    It should work when instantiating the SR-FF in structural code.

    Did you notice, that the VGA controller from Enoch O. Hwang's website www.cs.lasierra.edu/~ehwang is generally using "behavioral" coding? To my opinion it's much more functional and better readable.



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    sr flip flop in vhdl

    yeah, i did notice, thank you.. but i am not sure will it work if i will just copy and paste it to my ISE...for synthesation.. also pins mustbe assigned.. thats why i decided to build everything from scratch in structural code, but refering to the schematics of Enoch.



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    flip flop vhdl code

    I would expect the Altera example to work with Xilinx as well, cause the VGA controller itself uses only common VHDL constructs. With your "structural" description, you should have an understanding which structural elements are actually available in FPGA. These are not gates rather than LUT based logic blocks, where a D-FF is an elementary function.

    Ignoring these facts, you could e. g. cause the HDL compiler to use a combinational logic loop instead of a flipflop, possibly not operational because of timing problems.



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    Re: vhdl code for sr flip flop

    I have compiled structural SR FF code and came to know,
    1. you have added signal "clear" in Structural_SR_FF, why? even the signal is not referrred anywhere else?



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