Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Retiming in DC compiler

Status
Not open for further replies.
A

amoghsd_86

Newbie level 3
Joined
Feb 28, 2008
Messages
3
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,301
I want this specific document on retiming in synopys DC compiler
"Design Compiler reference manual: register retiming"

Please post the manual if you have.
 

Should I put any specific command or directive in the script so that Synopsys DC-Compiler will implement registers re-timing during its optimization phase?

Will the DC-Compiler report that it has used/implemented re-timing during the logic synthesis?

In the LEC, how should I support the re-timed designs? Are there any special commands / techniques?

Thank you!
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top