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Bias voltage in a fully differential cascode opamp

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AnnaA

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differential cascode

Hi,

I am trying to design a fully differential cascode opamp with common mode feedback. I have read Razavi, Holberg and Johns and I have a schematic but I can not find anywhere how to decide the values of the biasvoltages. Can anyone tell me where to find information about the values of the biasvoltages.

Anna
 

bias voltage cascode

the value of bias voltage is just to keep the ckt work under proper DC operating point.
Maybe you can try from this.
 

As was already said, there is no 100% correct answer for the bias voltage value that works for every single cascode amp. It totally depends on the process, how you size devices, what current the amp is running at etc. The whole idea in biasing a folded cascode is to ensure all the devices stay in saturation. If any of your devices go into triode, it is going to kill your gain. Hence the bias voltage needs to whatever voltage keeps your devices in saturation. It is really that simple.
 

A saturated transistor doesn't have any gain. A transistor that is biased to operate in its linear region has lots of gain.
 

If your MOS transistor goes linear, it is going to kill your gain. Don't confuse it with a bipolar device where you want that to run in the active region(thus it has high gain). Saturation for a bipolar device is bad for gain. If you take a MOS cascode mirror and put the cascode device in its linear region your output impedance will significantly decrease. The idea of a folded cascode is your output stage is cascoded, thus has high output impedance. Hence it's gain is very high. ANy device that goes linear in the cascode stage is going to kill your gain.
 

AnnaA said:
Hi,

I am trying to design a fully differential cascode opamp with common mode feedback. I have read Razavi, Holberg and Johns and I have a schematic but I can not find anywhere how to decide the values of the biasvoltages. Can anyone tell me where to find information about the values of the biasvoltages.

Anna
Click to expand...

From Professor Calvin Plett

https://www.doe.carleton.ca/~cp/analog/foldn.html


The Last Semester I made a NMOS input fully differential folded cascode.

Make all calculations to put the FETs in active region with Signal caracteristics that you need (gain, output resistance, stability (output capacitance is responsible for the dominant pole), etc).

Choose the correct biasing network.

Think that you have many currents dependent by some factor, then you need to mirror currents.

Then take care with possible DC imbalances that appears in simulation and after tapeout: different currents in mirror due to finite output resistance, VTH, W, L, etc
 

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