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About the Layout Style

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AMS2007

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Hi All,
In my attached file as you see, for example ,
There are a lot of Well and Substrate Contact.
At this kind of layout style like filling Contacts in empty space,
What are merits and demerits?

Thanks in advance..
**broken link removed**
 

where is the attachment?
 

Hi,

The merits that you can get in this kind of layout style are:
* good isolation for both devices nmos/pmos.
* you avoid latch-up problem

demerit:
* chip real estate issue
* added parasitic resistance/capacitance

;-)
 

How about remove the body contact of the big power plate?
Isn't it better for substrate noise isolation? :D
 

Thank for fixrouter4400's answer.

But, in your Answer I can't understand that we get good isolation as the merits.
Could you explain to me in more detail?


I have attached another example below.

Type A is general layout style. Left & right building blocks have some distances to keep block isolation.
Type B is contact filled layout style. I have inserted some contacts to fill the space.

In this point, I agree with Pansoo's idea.

Thanks

**broken link removed**
 

hello

I Think if u add decoupling caps on the supply rails at this distance "layout style A", the layout in this case will withstand with noise
 

Hi AMS2007,

Yes it is true that by surrounding the pmos with an nwell ring connected to power line and surrounding the nmos with substrate ring connected to ground line will give you a good isolation for both transistors...but in general this rings are not much of use because as research showed. The stray electrons and holes(minority carriers) travel deeply into the substrate and are not properly collected by the nwell and substrate ring. Never the less putting these guardring is better than leaving it open.

Cheers :)
 

I think instead of putting so much substrate contacts and wasting area, its better to put decap for power nodes.
The basic drc however checks for substrate contacts to be at regular intervals from reliability point of view.

Hope this helps.

Regards,
Sandeep
 

fixrouter4400 said:
Hi AMS2007,

Yes it is true that by surrounding the pmos with an nwell ring connected to power line and surrounding the nmos with substrate ring connected to ground line will give you a good isolation for both transistors...but in general this rings are not much of use because as research showed. The stray electrons and holes(minority carriers) travel deeply into the substrate and are not properly collected by the nwell and substrate ring. Never the less putting these guardring is better than leaving it open.

Cheers :)
Click to expand...

Learning more now! Thank you very much!
 

Pls refer to below link.
I think it is very similar subject.



:D
 

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