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DC : combinational timing loop

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wakaka

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timing loop detected

Hi all.
I've run a synthesis using design compiler. In the log file, it says that timing loop is detected. After i do a report_timing -loop, it shows that there are 4 timing loops.
I thought that after compile, DC will automatically located the timing loops and by disabling timing arc between pins 'CK' and 'Q', it will actually break the timing loops.

this is one of the timing loop from the report.
Code: 
 Startpoint: Ocore_0/div_core_0/U8/Y (internal pin)
  Endpoint: Ocore_0/div_core_0/U8/Y (internal pin)
  Path Group: (none)
  Path Type: max

  Point                                       Fanout       Cap     Trans      Incr       Path
  ----------------------------------------------------------------------------------------------
  Ocore_0/div_core_0/U8/Y (MX2X4)                                   1.60      0.00 #     0.00 r
  Ocore_0/div_core_0/dsp_clk (net)           8871      1001.00                0.00       0.00 r
  Ocore_0/div_core_0/dsp_clk (div_core)                                       0.00 #     0.00 r
  Ocore_0/CLKDIV_O_DSP_CLK (net)                       1001.00                0.00       0.00 r
  Ocore_0/ahb_top_0/HCLK (ahb_top)                                            0.00 #     0.00 r
  Ocore_0/ahb_top_0/HCLK (net)                         1001.00                0.00       0.00 r
  Ocore_0/ahb_top_0/ahb_apb_0/CLK (ahb_apb)                                   0.00 #     0.00 r
  Ocore_0/ahb_top_0/ahb_apb_0/CLK (net)                1001.00                0.00       0.00 r
  Ocore_0/ahb_top_0/ahb_apb_0/apb_top_0/PCLK (apb_top)                        0.00 #     0.00 r
  Ocore_0/ahb_top_0/ahb_apb_0/apb_top_0/PCLK (net)     1001.00                0.00       0.00 r
  Ocore_0/ahb_top_0/ahb_apb_0/apb_top_0/clkdiv_top_0/hclk (div_top)           0.00 #     0.00 r
  Ocore_0/ahb_top_0/ahb_apb_0/apb_top_0/clkdiv_top_0/hclk (net)  1001.00      0.00       0.00 r
  Ocore_0/ahb_top_0/ahb_apb_0/apb_top_0/clkdiv_top_0/div_regs_0/clk (div_regs)     0.00 #     0.00 r
  Ocore_0/ahb_top_0/ahb_apb_0/apb_top_0/clkdiv_top_0/div_regs_0/clk (net)  1001.00     0.00     0.00 r
  Ocore_0/ahb_top_0/ahb_apb_0/apb_top_0/clkdiv_top_0/div_regs_0/clks_sel_reg_0_/CK (DFFRHQX4)     1.60     0.00 #     0.00 r
  Ocore_0/ahb_top_0/ahb_apb_0/apb_top_0/clkdiv_top_0/div_regs_0/clks_sel_reg_0_/Q (DFFRHQX4)     0.00     0.37     0.37 f
  Ocore_0/ahb_top_0/ahb_apb_0/apb_top_0/clkdiv_top_0/div_regs_0/clks_sel[0] (net)     4     0.02     0.00     0.37 f
  Ocore_0/ahb_top_0/ahb_apb_0/apb_top_0/clkdiv_top_0/div_regs_0/clks_sel[0] (div_regs)     0.00     0.37 f
  Ocore_0/ahb_top_0/ahb_apb_0/apb_top_0/clkdiv_top_0/CLKDIV_PARAM[23] (net)     0.02     0.00     0.37 f
  Ocore_0/ahb_top_0/ahb_apb_0/apb_top_0/clkdiv_top_0/CLKDIV_PARAM[23] (div_top)     0.00     0.37 f
  Ocore_0/ahb_top_0/ahb_apb_0/apb_top_0/CLKDIV_PARAM[23] (net)     0.02       0.00       0.37 f
  Ocore_0/ahb_top_0/ahb_apb_0/apb_top_0/CLKDIV_PARAM[23] (apb_top)            0.00       0.37 f
  Ocore_0/ahb_top_0/ahb_apb_0/CLKDIV_PARAM[23] (net)      0.02                0.00       0.37 f
  Ocore_0/ahb_top_0/ahb_apb_0/CLKDIV_PARAM[23] (ahb_apb)                      0.00       0.37 f
  Ocore_0/ahb_top_0/CLKDIV_PARAM[23] (net)                0.02                0.00       0.37 f
  Ocore_0/ahb_top_0/CLKDIV_PARAM[23] (ahb_top)                                0.00       0.37 f
  Ocore_0/CLKDIV_PARAM[23] (net)                          0.02                0.00       0.37 f
  Ocore_0/div_core_0/CLKDIV_PARAM[23] (div_core)                              0.00       0.37 f
  Ocore_0/div_core_0/CLKDIV_PARAM[23] (net)               0.02                0.00       0.37 f
  Ocore_0/div_core_0/U4/S0 (MX2X1)                                  0.00      0.00       0.37 f
  Ocore_0/div_core_0/U4/Y (MX2X1)                                   0.16      0.24       0.61 r
  Ocore_0/div_core_0/n3 (net)                   1         0.01                0.00       0.61 r
  Ocore_0/div_core_0/U8/A (MX2X4)                                   0.16      0.00       0.61 r
  Ocore_0/div_core_0/U8/Y (MX2X4)                                   1.60   1642.04 #  1642.65 r
  Ocore_0/div_core_0/dsp_clk (net)           8871      1001.00                0.00    1642.65 r
  data arrival time                                                                   1642.65
  ----------------------------------------------------------------------------------------------
when i read the rtl code of the div_core.v, i found that there is a mux to choose the dsp_clk
Code: 
wire    mux_dsp_clk 		= (mux_dsp_clk_sel==2'h0)? 		crystal_clk : (mux_dsp_clk_sel==2'h1)? 		rtc_clk: pll_clk;
   dsp_clk = mux_dsp_clk;

What should i do to overcome it?
 

design compiler timing loop

Timing loops occur bcos u have statements in which the LHS is assigned itself in the RHS or a direct net is present in the RHS which is linked to LHS.
in ur case is mux_dsp_clk_sel associated with mux_dsp_clk anywhere in ur code????
by the way DC breaks the loops for which u have to set a variable in DC.
im not sure of the switch to be added....u can google it for info.
Regards
 

timing loop design compiler

is it the mux that cause the timing loop in the analysis?
should i

1. Inform the designer to edit the rtl codes?
2. set_disable_timing Ocore_0/div_core_0/U8 ?
3. set_case_analysis 0 Ocore_0/div_core_0/U8/S0

will this help?
Actually in real case, what should actually be done when there is timing loop in the design? Let say the designers has released rtl codes for synthesis. After synthesis, there exists timing loops, what should be done next?
 

synthesis timing loop

I am new to synthesis?can any one tell wat is the maning of timing loop?
 

report timing loop synthesis

Yes it should be the mux creating the problem.
Timing loops are to be essentially taken care in the RTL.
i faced an issue in which DC removed the timing loops but the same code when mapped to an FPGA couldnt tackle the issue.
I suggest you to better report the problem to the RTL designer an get it rectified.
u can also use the set_case_analysis if u r not having any plans to synthesis ur RTL to any different synthesis tool....

Regards
 
dc_shell timing loop synthesis

if i do set_case_analysis, let say the warning is missing, does that mean that the generated netlist is free of that timing loop? or the tool just ignore the timing loop by not reporting it?
THe mux is used to choose different clock source in different modes, can i do set_case_analysis to the select pin of the mux so that it is in Normal mode?
 

mux clock set_case_analysis

I have face the same problem. We change the design in the end.
But I still think the clock-mux design style is safe, if we set constraints on mux cell properly.
 

timing loop + rtl

wakaka said:
if i do set_case_analysis, let say the warning is missing, does that mean that the generated netlist is free of that timing loop? or the tool just ignore the timing loop by not reporting it?
THe mux is used to choose different clock source in different modes, can i do set_case_analysis to the select pin of the mux so that it is in Normal mode?
Click to expand...

set_case_analysis command, it will make the clock domain as false path. them will be constrainted as different clock domain. Of coz the loop will be broken.

and usually the mux 's timing we need not constraint it, because the mux's selection always tied to a constant in nomal mode. we can set the mux's clocks as false path to each other.

maybe we should add clock gating in DC .tcl :) right？
 

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