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Multi-input XOR Gate - principle?

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multi input xor

Hello,

I used to know this in school, but can't recall it now. I know that a two-input XOR gate gives a high output when the inputs are different.

But, what about a multi-input XOR gate and a multi-input XNOR gate.

Any help would be much appreciated.
 

multiple input xor gate

I don't think there is such a gate.
When you cascade XOR gates (like cascading 2-input ANDs and ORs), you get a parity generator/checker.
 

cascading xor gate

No actually it does exist. I remember having studied it in my LOGIC DESIGN AND SWITCHING THEÒRY lectures!

It either give a HIGH when the no. of highs at the inputs is even or (and this is where I am confused) when the no. of lows at the input is even.
 

xor principle

It gives 1 when the number of inputs at high logic level is ODD. XOR simply adds the inputs, with no carry.
 
multiple input xor

Hi,
A nice subject indeed. Here is the reference got from google for 'multi input XOR' refer, https://users.cs.jmu.edu/abzugcx/pu...-GRADUATE/New/Points-to-Ponder-for-Week-1.doc
As per the document, a multi input XOR outputs a High when its inputs are odd numbers of Highs and a Multi input Xnor outputs a high when its inputs contain an even number of highs.
Obviously, a multi input XOR is an Even parity generator and Xnor an Odd parity generator.
Some how intuitivevly I still feel that a multi input XOR should have been defined as a negative logic coincidence detector. It should have produced an output high if and only if one of the inputs is high. By the way, is there any logic for this function?
Regards,
Laktronics
 

logic for n input xor gate

Hello,

the multiple input XOR (odd parity checker) logical element is present as building block in programmable logic devices. In a graphical view of synthesized logic(technology map), a multiple input XOR gate represents this function.

The said negative coincidence or one-hot checker implies more complex logic than n-XOR, cause it can't be cascaded easily. Didn't yet see any symmetry properties of this logic. I prefer to "infer" it from a HDL bit count loop, the compiler should choose an implementation.

Regards,
Frank
 

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