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How to convert Verilog code to block diagram or schematics?

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mhamed

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verilog to schematic

Hey,
I am almost new to hardware design. I have a Verilog project written in Al.tra Qua.rtus II. It is so hard to go through the codes. I wonder if there is a software which can convert this project to a block diagram or schematic.
 

Re: verilog to schematic

if you could use the code and synthesize it then the synthesizer will give you the architecture of the code as implemented on hardware...
 

Re: verilog to schematic

Hello,

you are referring to Quartus RTL viewer. But it's view hasn't a touch of HDL to my opinion. Of course you could produce *.bdf graphics, that look as confuse as RTL viewer output (or should say, you are hopefully not able to), but I believe, that's not what mhamed is looking for.

If you have the design in mind and want to check a detail of implementation, then RTL viewer could be helpful and you are able to navigate. The good thing with RTL viewer is, that it preserves hierarchies.

Thus I think, for the project there is no way but learning to read the Verilog code. If it's not in an appropriate readable form, then to extract the basic structure and algoritms on your own.

Regards,
Frank
 

verilog to schematic

Hello
I think you can have a try for the fpga advantage of Mentor or the active-hdl of aldec. These tools can import verilog or vhdl source and translate them to schematic. And you can have a try for the novas.
 

Re: verilog to schematic

Hey,

Are you sure Active-HDL can convert .v codes to schematic?
I know it can do it inversely, i.e. you can plot a schematic in active-HDL and it will provide you the base of your verilog codes (input, output, reg, ...), but I couldnot find what I wanted.
I am sure there should be a program which can convert verilog codes to schematic, it isn't so hard.
 

Re: verilog to schematic

You can use Synplicity tool (Synplify/pro) as an RTL sythesis engine and/or RTL viewer in structural and gate level schematic. Agreed with FvM that you'd better off learning the in and out of the RTL language iso the schematic version.
Cheers,
-s
 

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