Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

[SOLVED] CPLD clock source question

Status
Not open for further replies.

LaszloF

Member level 2
Joined
Sep 12, 2007
Messages
50
Helped
3
Reputation
6
Reaction score
3
Trophy points
1,288
Location
Romania
Activity points
1,570
cpld clock input

Hy,

I am new in the CPLD/FPGA world, I want to make a simple development board for
Lattice Mach4, my question is, is it necessary a clock source for the cpld, or just in case of state machines? A simple combinational asyncron implementation would work without a clock source or not?

Sorry if the question seems stupid, or to obvious.

Regards,
Laszlo
 

lattice mach4 schematic

hi
can u be bit clear, what you want to do? CPLD is a device onto which you can port your FSM or any other design, but if this design requires clock source then you'll have to give it to one of cpld pin as input.
Manasi
 

epm7128s

I wan to make some simple projects for start-up, the M464/32 CPLD 2 CLK inputs for the internal macro cells and logics. For example if I want to implement a simple asyncron logic based on a truth table do I need to connect some clock source, or just in case of state machines?

I have experience with microcontrollers, the CPLD/FPGA is very new to me.
 

connecting clock to cpld

Hello,

you don't need a clock for asynchronous logic, but synchronous can extend your designs functionality. Thus I would provide an option for an onboard clock, could be a socket for a crystal oscillator if you need it later. For an eval circuit, also manual input (pushbutton, switches) and output (some LED indicators) could be meaningful.

Regards,
Frank
 

    LaszloF

    Points: 2
    Helpful Answer Positive Rating
clock source 74hc

Thanks for the quick answers, I will keep them in mind.
 

does cpld workes without clock

Hi,

CPLD is not having any clock source inside. Whatever you connect to CPLD clock pin will become the clock for the CPLD.

If you need more details don't hesitate to contact me.

Regards,

N.Muralidhara
CRL-BEL
 

connecting to clock source fpga

Any experiment board should use a clock source.
If your cpld has enaugh flip flops use an integrated crystal oscilator with a frequency between 4MHz and 50MHz, and you will use flip flops to divide it.

In any way you will never use a 555 ic to give clock to CPLD/FPGA. Also hardly avoid to use 74ls ics to drive the clock input. The reason is that they have rise-fall time that is greater than the maximum acceptable from the cpld/fpga and the cpld/fpga will do wrong-unexpected things...
If you want to use a 555 to give pulses to the cpld/fpga use a high speed buffer like the gates of the 74fXX series. If you cant fint 74fxx use 74hc. Of cource no word to say connection between Cd4xxx and cpld/fpga
 

cpld clock

I suggest it's better to have a clock source on your board. If you don't need it you will lose one pin, but if you need a clock source you will lose a board.
 

cpld clock crystal circuit

Hi,

I am also new to CPLDs and ask a question similar to above.

I have just bought a CPLD kit that has an Altera EPM7128S CPLD on it and LEDs, buttons, RS-232

interface, 7-segemnt displays. I have attached a schematic of this kit.

Also, there is a 47B47 microcontroller on the board that is said to supply the clock for CPLD.

The clock frequency is controlled by a potentiometer connected to analog input of the

microcontroller. Simply, microcontroller gives a clock to CPLD that depends on the

potentiometer's value. All are OK.

But since I am also new to CPLD, and I have looked at the datasheet of the CPLD, there are 4 pins

that I want to understand.

1. INPUT/GCLK1
2. INPUT/OE1
3. INPUT/OE2/GCLK2
4. INPUT/~GCLR

*I think, I've to give logic 1 to OE1 and OE2 (to enable output, whatever circuit I build), is it

correct?

*What is the functionality of INPUT/~GCLR

*From the replies to this posts, I understand that I can set any I/O pin of CPLD as a clk pin.

But why is there a INPUT/GCLK1 pin? It is also marked in the datasheet?

Thanks for reading this long question list;)

Regards
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top