help needed in readmemb(....) verilog system task ......

readmemb

hi all

im using the ISE simulator for modelling of the modules involved in my project and i want the data to be read/write from/on the files ...

my question is : in the format of the readmemb("file_name",memory name,..) where is that file_name located ... will that be on the desktop OR in the c:/xilinx/..... OR where ? plz note that im using ISE simulator ... will taht be same for SIMULINK ?

waiting for the solution...
regards
Syed

verilog readmem

Previously I had trouble with the variations of "readmem". A testbench from last year contained the following comment.

// Old commands for using ASCII hex input files
// Pull the VLIW into the temporary memory array
// $readmemh("sample.hex", tmpMem, 0);

That testbench needed binary input data. I solved the problems and got it to work as such:

// First open the file for reading
file = $fopen("code.vec", "r");
$ferror(file, error);
if (error != 0)
$display("\nFile Open Failed with Error Code = %x", error);


// Pull next binary from file
return_value = $fread( mem, file);
if (return_value !=1)
error = 1;


Hope this helps.

----- Steve

readmem verilog

Hi
thank for ur reply but my question is WHERE IS THAT "code.vec" file defined ? im using modelsim 5.7 for almost 2 days and hav used ISE simulator for almost a week and couldnt find the solution

where the INPUT FILE is kept and compiled ?

I hope u understand my question

Thanks

readmemb verilog

In my case the input file "code.vec" is stored in the same folder as the testbench. This is working fine for several designs which I simulate with ModelSim.

Everyone has there own setup ideas for ModelSim. My particular setup is to copy all the source code, vector files, and and testbench into a common folder. I point ModelSim at that folder. The ModelSim program will create a subdirectory called "work" which contains its own data and compiled versions of my code. I do not use this folder for any actual FPGA builds. The reason is that ModelSim has a nasty habit of trashing its folder and project on a crash. By having my FPGA build in Xilinx separate, I am able to quickly recover.

Use the $fread and $ferror commands from my previous post. If you do not have an error on opening the file, then the issue is NOT where the file is but reading from the already open file.

---- Steve

Added after 1 hours 12 minutes:

A couple other things occurred to me.

1. I checked my project settings. Under each source code file, you can choose the language version to use. I am writing in Verilog and I chose the "default" setting rather an explicitly choosing the Verilog version.
2. If you are new to ModelSim, it has a rather annoying feature. If you add an existing source code file, then it has two options. A: Reference from current location, or B: Copy to Project Directory. I have been burnt several times by choosing the "Copy to Project Directory" . When you choose this, you MUST use ModelSim to do ALL future edits. The reason is it copies the file to a subfolder in the project directory and does NOT monitor when the original file has changed. Therefore, you end up building with the old original file and not the new edits, so nothing you try ever fixes anything. When you change a source code file, the tree view MUST should this file changing from a green check mark to a blue question mark. It can take a few seconds for the PC to recognize the change, but it must change. If editting files do not show up with the question mark, then it is NOT building with the file you are editting.

---- Steve