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why do test clocks have to be balanced during Cts ?

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test clocks

hallo, why do test clks have to be balanced during Cts. can they not skew on tester machine
 

test clocks

Usually testers cannot fiddle with the skew.

Also, your design may have chains that move from one clock domain to another in test mode...

so it makes a lot of sense if they are balanced.
 

Re: test clocks

Hi,

Usually testers are high samplers, if there is any jitter, measurement may not be correct.


If you need more details, contact me.

Regards,

N.Muralidhara
 

test clocks

I am not sure if testclk need to be CTS'd at all. The functional clocks in design are distributed to all the flop in design and need to be CTS'd. testclks are just muxed with functional clocks much before it reaches the point from where onwards CTS starts. So testclk sees the same CTS depth/skew as functional clock.

Further from tester, you can adjust skew between two testclks, but not the skew between two endpoints running off the same testclk.
 

test clocks

Unless guided otherwise, LogicVision muxes all clock domains into one test clock. If the test clock is not balanced then there is no way your test patterns will match.
 

test clocks

Test clock shoule be balanced in most scenarios, the
difficult is to select the balance point for many clocks which will drive the same sumodules under
different chip operation mode.

Chiou
 

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