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Modelsim/PE is the officially supported simulator for Xilinx and Altera tool flows. This means several things:
1) both Xilinx and Altera qualify their simulation/design-libraries for the Modelsim simulator.
2) Quartus-II and ISE/Webpack can generate testbench (automation) scripts compatible with Modelsim, making push-button invocation easy.
Aldec's Active-HDL doesn't have this "official" level of support. But everyone who has used ActiveHDL, raves about it (i.e. loves it.) It's faster (compared to Modelsim/PE), has a better GUI, and as of today, has comparable language support (Systemverilog/Verilog/VHDL.) Once upon a time, device-simulation libraries were very picky about the simulator -- For the most part, those kinds of problems are a thing of the past. No one has complained about any major incompatibilities between ActiveHDL's simulator-engine, and FPGA-simulation libraries.
I lean toward Systemverilog myself, so I have been watching Active-HDL since v7.2. 7.2 did not support enough Systemverilog to really be useful. 7.3 is almost caught up with Modelsim/PE 6.3 -- only critical thing missing from ActiveHDL is Systemverilog package/endpackage. Still, Modelsim/PE's Systemverilog support ism ore "polished" (i.e. fewer quirks), probably because it benefits from the Mentor's commitment to Modelsim/SE, which is an (expensive) ASIC signoff-grade simulator.
Beyond that, you just have to test both simulators for yourself, and see which one works better for you.
You can download a free 20-day evalation from Aldec's website.
For Modelsim/PE, you have to email Mentor Graphics for an evaluation license-key.
modelsim is so primitive it is hard to beleive why it is so popular. (microsoft ?)
what mentor does today is just to take this old software and criple it to se, pe, xe , starter, xilinx , altera versions.
the only thing they do is put loop delays inside.
every new version they come up with force you to compile all your files and packages.
and if you are not an expert you will find yourself cursing for hours.
every new version they come up with force you to compile all your files and packages. and if you are not an expert you will find yourself cursing for hours.
If someone writes all your own packages, then it is reasonable to expect that same person to also maintain compilation-scripts to rebuild the library, whenever necessary.
I agree it's annoying, but Modelsim has to move forward. And besides, most of the time, you only have to recompile when moving to a new major version (6.2 -> 6.3)
It's funny you say that. I was asking myself why I don't like Modelsim/PE's GUI, and I could not quite come up with a reason. Your sentence hits the jackpot -- the tcl-built interface is terrible in terms of responsiveness and robustness. Half the time, I can 'outclick' the interface. For example, if I open to many HDL files in the editor, it's possible to click the 'close' button on each file-tab fast enough, to crash the program. (I'm on a 3.0 GHz Intel Core 2 Duo, so my CPU isn't the problem.)
Aldec ActiveHDL also uses tcl, but their interface is so much more robust, and responsive.
One last thing, it seems like all these Windows HDL simulators work best on a dual-monitor system. On just one monitor, I find myself constantly re-arranging the main program-window, and waveform viewer-window. I haven't found a good way to manage my desktop screen-space on a single monitor.
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