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Interrupt handling in MCUs

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Is it OK to provide a slow signal on the interrupt pin of an 8051 derivative. I have an application where I have provide the signal to an 89C51 from a mechanical limit switch. I have used capacitors to chack debounce but the slope is now slow (it takes about 100us from high to low). I can't use a schmitt trigger or even a buffer to speed it up since the PCB is already designed and I cant make any changes now. I want to know if the interrupt will still work correctly with a slow edge signal
 

I would highly recomend to use a schmitt trigger circuit when connecting signals with slow rise/fall to the interrupt inputs of an 8051.

The CPU could see multiple interrups with a high frequency while the signal is in an undefined state (neither logical high nor logical low).

But I would try it in practice maybe the interrupt inputs have a schmitt trigger behavour :)

Just my two cents ...
 

Hi,
you can debounce by software.
Normally slow signals can be triggered to with an interrupt. The moment when the trigger occurs is not precise to the edge of the signal any more. This can now drift by temperature etc.

One thing you can do is leave away your capacitor. when first receiving a rising edge you can disable your interrupt and reenable after a certain timeout period. if the signal than is stable on high level you can reprogram trigger direction to high-low transition. and so on.

Do you really need an interrupt to test a switch ???

hope it helps,

aOxOmOx
 

I do need interrupt since I have to measure the RPM of a shaft recisely.

My question is that when a signal is falling slowly (negative edge trigger interrupt) but steadily, the interrupt logic will only see the negative edge once. Or is it.
 

But what if you will use level triggered interrupt . The soec sayss the only requirements - external interrupt signal must be dissappeared before ISR touine will be finished , otherwise new interrupt will be generated .

When interrupt happened you can in ISR block the interrupt from this source and reactivate it after predefined time to ensure that no false interrupts will be happened .
 

It is NOT. 8051 checks edge interrupts by checking logic level on INTx. If on last cycle, INTx is 1 and on current cycle is 0 then interrupt occur. However, your signal is slowly falling, it may be have undefined logic level on last cycle. Therefore, ISR will not occur. Checking datasheet for interrupt timing.
 

hi .. i would also debouce by sw ... iow disabel int after activation a reenable it after some time ... this will limit your max rpm but i think not very dramatically ... see your 'bouce' effect on scope and set time. anyway the debouce time shuld be much much smaller then period of your signal

regards

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