Can I use "FOR LOOP" using xilinx XST tool under

xilinx for loop

I have used if statements for most of the case. Now I have seen the use of "For-loop and While loop" under templates in XILINX ISE8.2 which uses xst synthesizer. But when I write program using "for-loop", I didn't get the output or rather that looping isn't executing at all. I did write in perfect procedure. Currently I'm only able to use "If-Else, when-Case" statements. Is ther any other statements which I can use in xilinx xst?. Please note me out. Thankz

for loop syntax in xilinx

I think you are talking about VHDL, yes?

Maybe you aren't using the 'for' loop correctly. Remember that 'for' loops in HDL work differently than 'for' loops in a software language such as C. If you can show us an example of the code that isn't working for you, maybe someone here can help you debug it.

xilinx vhdl for loop

Well to append to the comment from echo47 "the master" , for loops with variable range are not synthesizable. For loops can only be used in a design with constant range of iteration

for loop in xilinx

Thanks!. Given below are the codes that I used for checking the For-Loop statements operation. The iterations of these statements were taken from the templates of Xilinx's ISE8.2i under "Synthesis Constructs-Loop Statements"
Please point me out why the below statements didn't work out. Any statements written inside the For Loop seemed to be never executed.


entity For_loop is
Port ( clk : in STD_LOGIC;
led1 : out STD_LOGIC;
led2 : OUT STD_LOGIC);
end For_loop;

architecture Behavioral of For_loop is
SIGNAL clk_slow : STD_LOGIC;
SIGNAL temp : STD_LOGIC:='0';
begin
-------------Slow clock generator------------------
-- This process generates approx 1 sec clock from 20MHz crytal clock at Gclk
--------------------------------------------------------
PROCESS(clk) IS
VARIABLE i : INTEGER := 0;

BEGIN

IF RISING_EDGE(clk) THEN
i:=i+1;
IF(i =10000000) THEN
temp <= NOT(temp);
clk_slow <= temp;
i := 0;
END IF;
END IF;
END PROCESS;
----------------------------
PROCESS(clk_slow,temp) IS
VARIABLE temp1 :STD_LOGIC:='0';
VARIABLE temp2 :STD_LOGIC:='0';
VARIABLE f : INTEGER:=1;
BEGIN

IF RISING_EDGE(clk_slow) THEN

FOR i IN 1 TO 5 LOOP
temp1:= NOT(pulse);
led1 <= temp;
f:= f+1;
END LOOP;

IF(f>=5) THEN
led2 <= temp;
END IF;
END IF;

END PROCESS;
END Behavioral;
-------------------------------------

Added after 7 minutes:

xstal said:

Well to append to the comment from echo47 "the master" , for loops with variable range are not synthesizable. For loops can only be used in a design with constant range of iteration

Click to expand...

Do you mean the integer for loop range should be defined in constant?. But no synthesis errors appeared when I declared it as variable!

if else in xilinx

you should change your statement:
IF(i =10000000) THEN
Now it is possible to go to undefined values, when you change it to
if i<01111111, it isn't possible to go to undefined state's

implementing for loop in xilinx

What is signal 'pulse'? I don't see it defined anywhere.

I'm no VHDL expert, but your 'for' loop resembles a software programming loop. Software loops and HDL loops work differently. I'm not sure the best way to describe the difference, but an HDL 'for' loop doesn't really go round-and-round executing statements sequentially like in a computer program. Instead, an HDL 'for' loop creates multiple copies of the logic inside the loop.

xilinx use a clock for loop

Thanks echo!, but this is how the syntax has been described in the templates in that Xilinx ISE software. I think I gotta give up. In case, you find some idea about it by experience, then do make a note. Thanks

Added after 1 minutes:

maartenh said:

you should change your statement:
IF(i =10000000) THEN
Now it is possible to go to undefined values, when you change it to
if i<01111111, it isn't possible to go to undefined state's

Click to expand...

The value 1000000 is an integer. And to your point, this is just a clock divider which generates pulses in seconds.They are very slow.

Added after 1 minutes:

echo47 said:

What is signal 'pulse'? I don't see it defined anywhere.

Click to expand...

I have forgotten to declare it in signals under architecture. Pulse is just a bit register

signal pulse : STD_LOGIC:='0';