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Help me with FPGA coding (holdtime issues)

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wakaka

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Help FPGA holdtime

Hi, currently I'm learning FPGA using xilinx ISE 8.2.

XIN = 32Mhz
I have a design which has clock pin XIN. I have a DCM in my design which divide the master clock by 2, so the CLKDV = 16Mhz.

I have
assign XTAL_OUT = XIN;

In the ucf file I have define the constraints as :
NET "XIN" TNM_NET = "XIN";
TIMESPEC "TS_XIN" = PERIOD "XIN" 31.25 ns HIGH 50 %;

so i assume the tool will generate the DCM CLKDV timing constraints.
After synthesis and implementation i get a hold time violation.

Code: 
Hold Violation:         -6.910ns (requirement - (clock path skew + uncertainty - data path))
  Source:               up_core_0/u_8052/sfr1/acc1/data_out_4 (FF)
  Destination:          up_core_0/up_glue_0/UBOOT_ADR_U1_4 (FF)
  Requirement:          0.000ns
  Data Path Delay:      0.994ns (Levels of Logic = 1)
  Positive Clock Path Skew: 7.879ns
  Source Clock:         XTAL_OUT_OBUF rising at 0.000ns
  Destination Clock:    up_core_0/up_glue_0/regwr_clk rising at 62.500ns

Y i got this violation? how to overcome it?
thanks.
 

Help FPGA holdtime

is xtal_out is deducated clock output???
 

Help FPGA holdtime

wat u mean by deducted output?

I just assign XTAL_OUT = XIN
 

Re: Help FPGA holdtime

You got the time violation because the time you need is exceeds the ability of the routing. If you look at the timing report it shows you that once you subtract the time for the clock path timing, the uncertantity value, and the datapath, you dont have enough time left to meet your requirement.

This is where you actually have to take into consideration your routing efforts. You are going to have to adjust somewhere in your design to meet your timing.

E
 

Help FPGA holdtime

I think he's asking why "Requirement" is 0.000ns. It seems like something went wrong in the constraint arithmetic, but I'm not sure what caused it. It would help to see the HDL code.
 

Re: Help FPGA holdtime

THe hdl code is long, i cant post it in here.
From the timing report, the destination clock is regwr_clk.

From the hdl code, regwr_clk has a mux to select between Test clk and XIN.

Code: 
wire	regwr_clk = TEST ? XIN : TEST_CLK;

whereas the XTAL_OUT is connected to XIN.

Code: 
assign XTAL_OUT = XIN

For the timing constraints, I only set one timing constraint, others are just pin assignment constraints.
Code: 
NET "XIN" TNM_NET = "XIN";
TIMESPEC "TS_XIN" = PERIOD "XIN" 31.25 ns HIGH 50 %;

When i do my synthesis, implementation, i got hold time violation on that which i'm not sure
(i)why and
(ii)how to overcome it. And also how to determine the
(iii)Requirement: 0.000ns
(iv)Positive Clock Path Skew: 7.879ns

Plz help, thanks.
 

Help FPGA holdtime

Instead of using that multiplexer expression for regwr_clk, try using a BUFGMUX primitive (see your ISE Libraries Guide). That will ensure the mux is implemented with the FPGA's dedicated clock multiplexer/buffer, and the clock is routed through a low-skew global clock net.
 

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