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How to test or simulate the jitter of LVDS TX ?

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fanrourou

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LVDS design

Hi , every one :
Does anyone kniow how to test or simulat the jitter of LVDS TX ?
and what are the structures of LVDS TX for low supply voltage ?
 

LVDS design

LVDS Tx design is pretty much standardized. You can look for papers or standards from National Semiconductor.

You can also check IEEE papers. If you can't find them, let me know.

LVDS driver basically differs from each other in a few ways:

1. whether you cascode your current source?
2. whether you do cmfb?

If you are low voltage supply, you might skip cascode. If you have no requirement on common mode noise, you can skip cmfb.
 

Re: LVDS design

neoflash :
I need IEEE papers on LVDS , but I can't downlowd .
Would you be kind enough send me ?
My email :
xihuwang@126.com
 

Re: LVDS design

pls wait until next week working days.
 


LVDS design

Please post it on the board instead of sending the paper individually....
 

LVDS design

a lot of IEEE paper talk about this
 

Re: LVDS design

fanrourou said:
neoflash :
I need IEEE papers on LVDS , but I can't downlowd .
Would you be kind enough send me ?
My email :
xihuwang(at)126.com
Click to expand...

Here you go.
 

Re: LVDS design

concerning the jitter - as jitter depends on the noise created in the TX driver stage you can do a transient noise simulation with mmsim/spectre from cadence - if you use cadence tools ...

after running the transient noise simulation with a pseudo-random-bit-generator or just a pulse source you can make an eye_diagram with the calculator and you'll get what you want ...

the other way to get information about jitter is to use pss and pnoise ...
 

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