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How to modeling the kT/C noise with VerilogA

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fatcat1205

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Hi, everybody.

I am simulating a delta-sigma ADC with Verilog-A model. I try to add the kT/C noise into the transient analysis. Does anybody know how to set up a kT/C noise verilogA model, which support the transient analysis.

Thanks very much.
 

Hi, everybody. I have found a method to generate the white noise in Verilog-A. If I let the power density of that white noise equals to KT/C, It may be somehow to represent the KT/C noise, is that alright?

When given 1p F capacitor, the mean square root of noise with such code is 6.079e-5V. That's quite close to the theoretical value 6.43e-5V
 
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    elle88

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resently, i recieved some letters to ask me how to determin the numbers of generated samples. Actualy, i determined the numbers by setting the simulation steps. for example, if i set the transient analysis time as 1ms, and simulation step as 1us, the 1ms/1us = 1000 samples will be generated. This is because that, during every simulation step, the simulator visits the noise module, and make it generate a random number. So the number of samples is determined by the simulation steps.

I hope this will be useful.

P.S a large number is needed to make the noise sample follows the distribtion.
 

This (what you are doing) has one major drawback:

You are using the funciton $rdist_normal to generate "certain" amount of noise energy. BUT its distribution across frequency (i.e. its frequency shape) is dependent on the simulation steps. It can have very high frequency components, or not.

So what is the problem?

The problem is if we filter that KT/C, you don't know what you get at the output.

Regards,
Hamid
 

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