question about crystal load capacitor

32khz crystal capacitor

I'm not clear about the meaning of the crystal load capacitor CL.

As in the reference manual, the crystal has following parameters: Ls, Rs, Cs for the series resonance, Cp as intrinsic shunt capacitor, then what's the Load capacitor CL meaning?

1. As a crystal intrinsic model parameter, just connected shunt to the Cp.
2. Modeling the parasitic effect on PCB board.
3. crystal oscillator IC has input capacitance CL.

which one is correct?

Regards

shunt load capacitor for crystal

Dear Sir :
In the paralle oscillation. The xin and xout mist coonect 2 cap , 10p 10p, it mean the cload is 20p..

crystal loading capacitors

These loading capacitors should be as small as possible and not bigger than the maximum allowed by the crystal manufacturer. Any loading capacitors will cause higher drive currents through the crystal and affect long term accuracy in critical timing circuits. Naturally their value also alter the oscillating frequency slightly. Typical power dissipation of a 32.768kHz watch type crystal should be kept under 1uW. So the current allowed through such crystal is in the order of 45-100nA max!

crystal load capacitor

then who can tell me the CL physics meaning?


and my 1~3 which is correct?

xtal load capacitor cl

E-design said:

These loading capacitors should be as small as possible and not bigger than the maximum allowed by the crystal manufacturer. Any loading capacitors will cause higher drive currents through the crystal and affect long term accuracy in critical timing circuits. Naturally their value also alter the oscillating frequency slightly. Typical power dissipation of a 32.768kHz watch type crystal should be kept under 1uW. So the current allowed through such crystal is in the order of 45-100nA max!

Click to expand...

hi,
can you state it more in detail why "Any loading capacitors will cause higher drive currents through the crystal and affect long term accuracy" ?

thanks,
jeff

crystal power dissipation

In the common Pierce configuration used in IC's, the crystal power dissipation is defined as:

Pd ≈ 0.5(2Π x //freq x C-equiv x voltage swing)² x Rs

where C-equiv: is [C-holder + Cx{Cy/(Cx + Cy)}]

and Cx, Cy is the capacitance seen on terminal X and Y of the crystal.
Part of the Cx and Cy may be internal to the IC already.

The current flowing through the crystal internal Rs (series resistance, can be 20k - 50k+ for a 32.768kHz crystal) will heat up the crystal. If it is way too much it may even damage the crystal. Temperature changes will cause frequency drift.

Of course you will want to keep the crystal dissipation as low as possible and way below the max allowed by the manufacturer.

Look at the video by Jim Williams on measuring current drive for a 32kHz crystal
"Measure nanoamps to ensure.." on this page
**broken link removed**

cl crystal capacitor

and for my question, brothers?

I just design a 26MHz xtal osc chips, shoulda use external xtal model, I just don't know the CL parameter in the quartz xtal manufacutre manual, it should be included in the xtal model for my simulation, or shoulda be inluded as my circuit input capacitance?