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RF Synthesizer design ?

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mitgrace

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rf+synthesizer

Dear All :
I will design a RF Synthesizer , The reference clock is 32KHz. The VCO is 3G ,
And the Loop filter is embed in the IC . DOes any one have any comment ?
It's like the convertional PLL is not suit here , Any Comment ??
 

rf synthesizer

Hi,

Have you the different blocks, PFD, CP, VCO.. or you have to design these components too ?

VCO is 3 Ghz you mean ?
If it is so, don't you think that the report VCO_freq/ref_freq is big ?
 

rf synthesizer design

Dear master_picengineer :
This is a big problem for me. we see other prodcut do that, I don't which structure of RF synthesizer . they use it ? DO u have any comments ?
 

mitgrace is forgetting to say that he needs to systhesize FM band (roughly 100MHz). He will use 3GHz VCO most probably to integrate VCO tank in IC (we had past discussions in another topic). So the ratio FLO/FREF is not so high.
Mazz
 

Dear Mazz :
You are correct , The product is implemebt by other company. But we don't know why they use 32K input and L-C VCO is 3GHz, and embeded the loop filter.
We guess they use digiltal PLL , the L-C VCO is instead by L-C DCO , other block they using digital method to finish it. Actullay this is why we study it. Please reference si4701 datasheet. ANy comments ??
 

I suspect that the 32 kHz crystal is the cheapest available quartz xtal. To fit a LC oscillator on-chip, you need small L and C, so you have a high oscillator frequency. Integrated loop filter because then you stay on chip and don't have to worry about what a customer implements off chip, and it saves you a little money for external components.

Dave
www.keystoneradio.com
 

the reference frequency is too small
fractional-N PLL should be used
 

Silabs have their own PLL architecture which is DSPLL which is a PLL which have DSP part to control the phase noise performance , and also they may implemented the filter as a digital filter

about the 3 GHz VCO , they make this very high frequency so the all VCO can be integrated then use a set of dividers to get the desired frequency

khouly
 

Some detail on khouly post in www.silabs.com/public/documents/marcom_doc/mcoll/Timing/en/DSP_Driven_Clocks.PDF

Take care: it seem to me that they use this kind of PLL architecture not to generate local oscillator for radio applications (an there could be a lot of reasons for this). Looking at GSM PLL for example, I've seen only traditional approaches.

Based on my experience, the FM LO generation (for cellular application) can be fully integrated using a traditional PLL architecture.

I hope it can help.

Mazz
 

Difficult to design.

You should design a suitable loop filter.

Added after 1 minutes:

What the lock time of you system. if you don't care the lock time, may be easy.
 

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