Question on Transimpedance amplifier gain plot

Hi Guys,

I have question here. I have designed a transimpedance amplifier (TIA) which works at 1.25Gbps. I have run the AC simulation at the package level (wire-bonding model). Attached are the 2 plots of the gain fucntion. Bode1 is the gain function with the multiple ground pin and Bode2 is the gain function with single ground pin. If we look at the graphs, it shows that multiple pad of grounds causing no peaking the at -3dB bandwidth, i believe this is due to the LC inductance peaking issue. A few packages in parallel reduced the effective inductance compared to a single package which cause the peaking in Bode2. Can anybody give me the better explanation on this issue. Is in the manufacturing, having multiple ground pads (package) is recommended?

Thanks,
suria3

Your chip has some equivalent capacitance and vdd and gnd leads inductance, which means LC circuit with natural freq ω0=1/√LC . Also you have some resistivity form vdda lines... which actually helps in damping.
You can not change C, but you can try to decrease L, which means that ω0 will be shifted towards high freq... I dont know why there is not a peak at all.
Read Steyart's book... Integrated CMOS circuits for optical communications

So, pixel, is it a normal procedure in actual chip fabrication that there should be multiple of ground pin packages of TIA design in order to reduce the inductance effect? Thx.

I do think that reduce inductor removes the peaks. It's not bad to remove peak using multi VDD or VSS bonding. And you can use low L bonding wire or make it as short as possible.