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A question of Active Current Mirror

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patriot

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On pp.148-149 of Razavi's "Design of Analog CMOS Integrated Circuits"
I am confused that there is a conflict with KCL at Vout node. At another hand, as it is said in this part, the currents of M3 and M4 increase, how can i be possible to equal the current source Iss?
 

Hi,
In large signal behavior, the currents of M3 and M4 have the relation:
Im3 + Im4 = Iss
But in small signal behavior (the current source Iss is open circuit), this relation is not valid.
 

i see, but the active current mirror performs no inversion, If Im3 increase δI,Im4 will also increase δI, how can it comply with KCL law?

Added after 9 minutes:

As it is said in this paragraph, Im4 increase and Im2 decrease, how to explain this against KCl?
 

Hi,
About M3 and M4 again I emphasize, you souldn't consider the large signal behavior.
About M2 and M4, consider that there should be a load at the output (All the arguments about the circuit is done considering that there is a load at the output).
 

that is a fantastic question. My friend, your problem is that you are think of an "ideal" mos. there is no such thing out there. Remember, each transistor has ro due to channel length modulation. The current at Vout will flow through these two resistors. So, there is actually no problem.

Cheers
 

Hey,patriot!
It's also can be explained from the view of large signal point. The gate voltage of M3 forces the drain current of M4 to increase, but the current of M2 decreases. In other words, M4 has to sink identical low current with M2 while keep identical high |vgs| with M3. So, |vds| of M4 has to decrease due to channel length modulation. That's why vout increases.
Hope this can help you!
 

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