ESD Transistor: Why the pitch contacts of the Drain should..

Hi everyone,

I wonder why the pitch (contact to contact spacing) of the contacts of the Drain side of a ESD transistor should be more than the minimum. For example the minimum spacing is 0.22um but my chief engineer advised me to use 2um pitch. Please anyone help.....

Re: ESD Transistor: Why the pitch contacts of the Drain shou

Hi electronXwork,

I have never come across any paper etc. that would have recommended to use a larger pitch for the contacts in the drain region. Logically, it makes no sense as one would want to have as many contacts as possible. Maybe it was a misunderstanding and an extended drain region was suggested? That would make sense, as it is common practise to use an extended drain region as drift path for carriers. That way, you would have a larger spacing between gate and the first (if there are more than one) row of contacts parallel to the gate. Also, usually you have larger spacings between contacts and implant perimeters to ensure an even current distribution among the contacts. There are a lot of things to consider, maybe you should ask what was meant by the suggestion of your cheif engineer.

Regards,

Christian

You can reference the foundary ESD design rule to solve your problem.BR

Re: ESD Transistor: Why the pitch contacts of the Drain shou

ask your immediate superior; he knows it.

Re: ESD Transistor: Why the pitch contacts of the Drain shou

protonixs said:

ask your immediate superior; he knows it.

Click to expand...

You know it? I asked you.....


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Added after 3 minutes:

hionyeh said:

You can reference the foundary ESD design rule to solve your problem.BR

Click to expand...

My trainer said there are no design rule for this it is just a layout technique. I just can't understand well his explanation because he speaks japanese.

I have done this in the past and it adds resistance in series with the drain to limit the current and to add ballasting. This only works on a non-silicided process. The contacts are usually also drawn further away from the gate than minimum rules to also add resistance.

Re: ESD Transistor: Why the pitch contacts of the Drain shou

electronXwork said:

Hi everyone,

I wonder why the pitch (contact to contact spacing) of the contacts of the Drain side of a ESD transistor should be more than the minimum. For example the minimum spacing is 0.22um but my chief engineer advised me to use 2um pitch. Please anyone help.....

Click to expand...

The extended space have paracitic R, then makes the MOS more strong in ESD protection.

Re: ESD Transistor: Why the pitch contacts of the Drain shou

as this inverter work as amplifier. so to increase the out put resistance.

Yes, this parasite resistance will limit the current thru contacts to avoid contacts melt during ESD event.