Help me translate this Verilog code to VHDL

verilog to vhdl

Is anyone who can help me to translate this verilog code to vhdl?The code is:


module vga_controller(SynchClock,a,b,c,d,inRed,inGreen,inBlue,Red, Green, Blue,Hsynch,Vsynch,blank,synch,mem_address);
input SynchClock;
input a,b,c,d;
input[7:0] inRed, inGreen, inBlue;
output[7:0] Red, Green, Blue;
output Hsynch, Vsynch;
output blank,synch;
output reg [16:0] mem_address;

reg [7:0] Red=8'b00000000 , Green=8'b00000000, Blue=8'b00000000;
reg Vsynch=0, Hsynch=0;
reg blank=1,synch=1;
reg [19:0] x2=20'b00000000000000000000,y2=20'b00000000000000000000;

reg [9:0] Hcount=10'b0000000000, Vcount=10'b0000000000;
reg [9:0] PixelRow=10'b0000000000, PixelCol=10'b0000000000;

always @(negedge SynchClock) begin
blank= 1'b1;
synch = 1'b1;

if (Hcount == 799) Hcount =0;
else Hcount = Hcount + 1;
if (Hcount >= 661 && Hcount <= 756) Hsynch = 0;
else Hsynch = 1;
if (Vcount >= 525 && Hcount >= 756) Vcount = 0;
else if (Hcount == 756) Vcount = Vcount + 1;
if (Vcount >= 491 && Vcount <= 493) Vsynch = 0;
else Vsynch = 1;
if (Hcount <= 640) PixelCol = Hcount;
if (Vcount <=480) PixelRow = Vcount;
if (Hcount <= 640 && Vcount <= 480) begin
if(a & b & c & d ) begin
if (PixelCol<=479 && PixelCol >=159 && PixelRow<=359 && PixelRow>=119) begin
mem_address = ((PixelRow-119)*320)+ PixelCol-159;
Red = inRed;
Green=inGreen;
Blue = inBlue;
end
else begin
Red = 8'b11111111;
Green = 8'b11111111;
Blue = 8'b11111111;
end
end

if(a & b & c & ~d ) begin
// if (PixelCol<=479 && PixelCol >=159 && PixelRow<=359 && PixelRow>=119) begin
x2=724*PixelCol/1024 + 724*PixelRow/1024;
y2=-724*PixelCol/1024 + 724*PixelRow/1024;
mem_address = ((y2-119)*320)+ x2-159;
Red = inRed;
Green=inGreen;
Blue = inBlue;
end
/* end
else begin
Red = 8'b11111111;
Green = 8'b11111111;
Blue = 8'b11111111;
end
*/
if(a & b & ~c & d ) begin
if (PixelCol <=159 && PixelRow<=439 && PixelRow>=119) begin
x2=PixelRow;
y2=-PixelCol;
mem_address = ((y2+159)*320)+ x2-119;
Red = inRed;
Green=inGreen;
Blue = inBlue;
end
else begin
Red = 8'b11111111;
Green = 8'b11111111;
Blue = 8'b11111111;
end
end
if(a & b & ~c & ~d ) begin
x2=-724*PixelCol/1024 + 724*PixelRow/1024;
y2=-724*PixelCol/1024 - 724*PixelRow/1024;
mem_address = ((y2-119)*320)+ x2-159;
Red = inRed;
Green=inGreen;
Blue = inBlue;
end
if(a & ~b & c & d ) begin
if (PixelCol <=159 && PixelRow<=119) begin
x2=-PixelCol;
y2=-PixelRow;
mem_address = ((y2+119)*320)+ x2+159;
Red = inRed;
Green=inGreen;
Blue = inBlue;
end
else begin
Red = 8'b11111111;
Green = 8'b11111111;
Blue = 8'b11111111;
end
end
if(a & ~b & c & ~d ) begin
x2=-724*PixelCol/1024 - 724*PixelRow/1024;
y2=724*PixelCol/1024 - 724*PixelRow/1024;
mem_address = ((y2-119)*320)+ x2-159;
Red = inRed;
Green=inGreen;
Blue = inBlue;
end
if(a & ~b & ~c & d ) begin
if (PixelCol<=399 && PixelCol >=159 && PixelRow<=119) begin
x2= - PixelRow;
y2= PixelCol;
mem_address = ((y2-159)*320)+ x2+119;
Red = inRed;
Green=inGreen;
Blue = inBlue;
end
else begin
Red = 8'b11111111;
Green = 8'b11111111;
Blue = 8'b11111111;
end
end
if(a & ~b & ~c & ~d ) begin
x2= 724*PixelCol/1024 - 724*PixelRow/1024;
y2= 724*PixelCol/1024 + 724*PixelRow/1024;
mem_address = ((y2-119)*320)+ x2-159;
Red = inRed;
Green=inGreen;
Blue = inBlue;
end
/* if(~a & b & c & d ) begin
if(~a & b & c & ~d ) begin
if(~a & b & ~c & d ) begin
if(~a & b & ~c & ~d ) begin
if(~a & ~b & c & d ) begin
if(~a & ~b & c & ~d ) begin
if(~a & ~b & ~c & d ) begin
if(~a & ~b & ~c & ~d ) begin
if(a & b & c & ~d ) begin
if(PixelCol < 320 && PixelRow > 240)begin//katw aristera xwris GREEN
mem_address = ((PixelRow - 240) * 320) + PixelCol;
Red = inRed;
Green = 8'b00000000;
Blue = inBlue;
end
if(PixelCol >= 320 && PixelRow <= 240)begin//panw deksia xwris BLUE
mem_address = (PixelRow * 320) + PixelCol - 320;
Red = inRed;
Green = inGreen;
Blue = 8'b00000000;
end
if(PixelCol >= 320 && PixelRow > 240)begin//katw deksia xwris RED
mem_address = ((PixelRow - 240) * 320) + PixelCol - 320;
Red = 8'b00000000;
Green = inGreen;
Blue = inBlue;
end
*/ end
else begin
Red = 8'b00000000;
Green = 8'b00000000;
Blue = 8'b00000000;
end
end
endmodule

Re: verilog to vhdl

Do you need a behavioral description or it's good for you also a structural one?

Re: verilog to vhdl

I need both of them as soon as possible.

Re: verilog to vhdl

No response yet???

verilog to vhdl

check this link:
**broken link removed**

Re: verilog to vhdl

this the document i am having that no the exact code for ur design but this is also the VGA interface in VHDL

Re: verilog to vhdl

maybe you can use x-hdl to change it

verilog to vhdl

some of the compilor support both, why convert?