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when u apply a current load step (i.e. from Iload=0 > Iload_max) and modeling the LDO with its thevinin equ. it will be a voltage source with a series output resistance , so the drop in the voltage will be Iload*Rout
Delta V2 is differential pair offset and feed back ratio. differential pair offset base on loop gain. Loop gain is depend on output current. The higher output current the less loop gain so offset will be bigger thus delta V2 become bigger.
it's load regulation error which is generated from the finite loop gain of the closed loop characteristics, like OPAMP configured in the closed loop, the "+" and "-" terminal has error =Vi/(1+Loop gain). and since during the heavy load of LDO, the ro is smaller than lightly load, so loop gain in heavy load is smaller than lightly load, so the error is bigger.
As you can see, when you apply that high current step from 0 to Imax, there is a transient and then the voltage set to a lower value by delta V2. This is because when you asks the circuit for high current, the output impedance lower itself to keep the same voltage, but, due to bandwidth, slew rate and parasitic issues, is stabilize at a voltage different than the former. This is like a PD controller, you'll have a steady state error. The same applies to a Imax to 0 current step, but in the opposite direction.
You can prove this by applying a low rise/fall current step to the output of the LDO. Delta V2 will be lower because the circuit has enough bandwidth and slew rate to response to a slow current transient. The spikes also will be reduced. So, finally, that drawing you upload is the worst case transient response for that LDO.
how about internal resgulator inside IC chips ? many IC have multi inside power , but can not use large Cap .. in cmos process use opa + Pmos
will cause system unstable ..
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