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what is the flase path and multiple path in physical design

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False path is an unused path which is not considered during timing analysis
for example take a multiplexer..it has so many signals conected for its interneal use only but when it comes to timing analysis it is not be going to use so that is the false path..........
like G1, G2_n or something like that u will see right or else read wakerly book there u will come to know the false path
 

if you have more logic between registers ...to over come that dalay we should use more than one clock cycle...that path is called multi cycle path
 

false path : this is a path which exists in ur design and u do not want the "timing tool" to check for timing on this path, cos u kno tht the timing chk is gonna fail !!

so instead of hte tool trying to meet the timing on this path( which is a waste) , u hv to specify it as a "false path"

ex: asynchronous clocks !!!

MCP :
 

synchronizers, or paths where signals which cross clock domains are usually added as false paths in the constraints.

a good example of multicycle path would be a pipelined path
 

more examples MCP :

1) when a slower clock domain in interacting with a faster clock domain & vice-versa

2) multiplier logic

3) pipe lined logics ( as mentioned above)

nemore additions ???
 

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