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while doing timing analysis you have option in the form where in one can optimize drvs especially. enable that switch. May be that can fix the problem to an extent.
The Transition viol is related to setup time. i,e to say, tht wen u fix the setup violations, the Transition violation gets fixed up to an extent
I assume that fixing DRC (as u mentioned ) is for the clock path !!
The CTS specification file has to be written properly to fix the violations.
the options like
1) buffer transition
2) sink transition
3) MaxSkew
4) NoGating
5) NO Buffer ..... all have to be provided exactly.
cos the options like "buffer type" and "buffer transition" values define the length & delays of the net(in Clock path) which the tool takes while performing the DRC checks ... !!!
Hi Priya_j,
DRV violation include three things
1.Max Cap
2.Max Tran
3.Max Fanout
First, one should fix Max cap, that you can do by including Max Cap statement in cts specification file.You assign cap value for a buffer by using this statement.Cap value you decide by looking int SDC.
Even you have Max Fanout statement in cts spec file,you give fanout value by looking into SDC and libraries.
After Max Cap is fixed mostly you will not have trans violation.
try fixDRCViolation -maxCap -maxTran -maxFanout after CTScommand in encounter console
As everyone has stated, if your are getting drv violations during cts then you need to tighten your cts constraints. What do you have set for transition/slew?
Regarding the document for Clock tree synthesis constraints : layout Requirement specification, request you to visit this link. This article explains the complete hand-off which needs to be given to the layout designer who performs, the clock tree synthesis.
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