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who can explain the symbol?

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shilixiang

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who can explain this ?
when i do LVS ,using diva , in output file net match,termial match,instance match ,but it alse has another unusual sentence,"16 net _list ambiguities are resolved by random selection", is it a problem?who can explain why output file has this sentence? thx a lot!
 

why it says that - you'd have to contact cadence
but it is not a problem.
 

Teddy said:
why it says that - you'd have to contact cadence
but it is not a problem.
Click to expand...
First thanks
I search the candence help docments,it should not be question.When circuit has symmetry structre,diva will use a Skill function to deceide which part of circuit will be first checked,so it has a selection . I also talk with my manager, he doesn't think it is a problem!
 

it's not a problem...

put labels in your schematic wires wherever there are networks (for example, strings of resistors in parallel) which are equivalent when interchanged, and then also label the same way the layout, then select the option for diva to use labels as references.

The msg will disappear then.
 

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