Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Why CML not CMOS for higher frequency divider?

Status
Not open for further replies.
frequency divider

the static CMOS is slower , and use full swing ,

in CML , u can make the core work in very low swing ,and this will give u tha ability to work in higher speeds , also the current steering is more faster than changing the load capacitors and at the output use buffer to convert the signal back to full swing ,

khouly
 
Re: frequency divider

In 0.18 and beyond, CMOS can definitely be used. However, it needs to be custom made using TSPC-like latches.

Cost: Uncontrollable power consumption and nigh supply noise ( due to CMOS rail-rail switching)
 

frequency divider

why uncontrollable power supply

Added after 50 seconds:

why uncontrollable power
 

Re: frequency divider

dinesh agarwal said:
why uncontrollable power supply

Added after 50 seconds:

why uncontrollable power
Click to expand...

means there is nothing limiting the current , while in CML, the current source used to limit it , at RF frequencies , it is better to use lower swing digital than the rail to rail one , supply noise will be very high , also CML may reach same frequency as the CMOS standard with lower current consumption , but as feature length of the tech. go down , this may be not true
 
Re: frequency divider

Can anyone suggest me a simple cml to cmos circuit
 

Try This:

 

    minhchau

    minhchau

    Points: 2
    Helpful Answer Positive Rating
Your dV/dt is fundamental. CML is better for two reasons.
One, at equal peak current, you have less swing (dV). Two,
you have a simpler input with one gate instead of two (C)
and its drain swings less (C, Miller).

At the limits, standard CMOS gate Idd begins to look like
peak current when the outputs never settle to the rails.
When you're up against it, CML and CMOS aren't that
different in power consumption.

There are some elegant stacked designs that do in one
stage, what would take several in bang-band combinatorial
CMOS.

CML downsides include noise margin and static power
consumption.
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top