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Again u say its urgent and problem is not clear here. Design in which form it is?. Block diagram or FSM or HDL or netlist or ...???.
I assume you have design in verilog format. Before encrypting, you need to know, who is going to use. Encryption is simulator dependent. It means that if it is encrypted using verilog-XL, then the recipient of that encrypted code must also have verilog-XL to simulate it with.
Verilog-XL procedure.
1. add `protected and `endprotected into your source code.
2. run " verilog yourfilename.v +protect "
The compiler will generate a file called "ourfilename.vp" for you.
So check your tool vendors for each encryption method.
hello sam.my design is in verilog hdl format.i want to verify it.i dont know how to do.i am using cadence NCsim for simulations.specman for verification
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