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FYP help...dual port block memory~~

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cloudz88

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generate sine wave using block ram in fpga

i need to pump in a sine wave using a dds.....so i can juz put sine = Din right??

but how can i store the values in the address??

can some1 explain to mi?
 

Which DDS are you referring to? A core perhaps?

If you only need the sinewave for HDL simulation, it's easier to use the sin() function.
 

ya..a core...
im using VHDL.....and im curious how can i store input into the dual ram address?
 

Which DDS core? Which FPGA? Store what input into the RAM?
Please explain the problem more clearly.

If you are using Xilinx XST, the XST User Guide explains how to write HDL code for dual-port RAM. See chapter "HDL Coding Techniques" section "RAMs and ROMs".
 

ok...my assignment is to generate a sine wave using the coregen(dds).....and pump the signal into another core(dual port blk memory). if im not wrong...i have to use DIN = SINE to pump the signal into the dual port ram.....but i dun realli know how can i store this signal in the dual port ram ADDR......

im currently using xilinx ISE 8.2 and modelsim XE III....doing a VHDL final yr project....

oh ya..btw echo47....do u rmb a guy called YenYu? a few months ago..he was doing a VHDL DDS project oso...and this semester...im assigned to carry on his work....hahs
 

I see you are now carrying the torch! ;)

Too bad you are required to use cores. You don't learn as much that way, and Xilinx cores are generally clumsy with mediocre performance.

I don't know much VHDL, and you didn't say exactly which cores you are using, but maybe this Verilog example will help you. When clocked at 100 MHz, it generates a 3 MHz sinewave, and then delays the sinewave through a dual-port RAM. Beware of long-line wrap.
Code: 
module top (clk, doutb);
  input                 clk;          // synthesis attribute PERIOD clk "100 MHz";
  wire           [11:0] sine;
  reg             [9:0] addra = 0;
  reg             [9:0] addrb = -50;  // use the RAM to delay the DDS signal
  output         [11:0] doutb;

  // Core "Direct Digital Synthesizer 5.0" settings: "dds", Sine, 100MHz, 72dB, 0.04Hz, disable RDY and RFD pins.
  dds dds1 (.DATA(32'h07AE147B), .WE(1'b1), .A(5'd0), .CLK(clk), .SINE(sine));

  // Core "Dual Port Block Memory 6.3" settings: "bram", width 12, depth 1024.
  bram bram1 (.addra(addra), .addrb(addrb), .clka(clk), .clkb(clk), .dina(sine), .dinb(12'd0), .douta(), .doutb(doutb), .wea(1'b1), .web(1'b0));

  always @ (posedge clk) begin
    addra <= addra + 1;
    addrb <= addrb + 1;
  end
endmodule
 

yes..thats the 2 core im using....dds v5 and dualport ram v6.3....

from ur codes...
always @ (posedge clk) begin
addra <= addra + 1;
addrb <= addrb + 1;

does that mean that there are alot of slots in addr??

issit possible for mi just to extract the data for example in addra slot 6 only?

how can i do it? addra(6) or watever??

sorriex...im quite new to this and i tried reading the data sheet but still dun realli understand how it works...

if there are many slots in addr....how many are there?

and in ur example...ur ram setting is width 12, depth 1024.......my supervisor tell mi to use 1024 depth but i dunno how much should i put as my width......im using a 500MHz dds with 10 bit sine wave...same as yenyu
 

I don't understand what you mean by "slots".

My addra and addrb registers are 10 bits each.

If you want to store 10-bit DDS data into the RAM, then you could simply configure the RAM core to be 10 bits wide. Common sense, yes?

500 MHz clock is too fast for a Virtex-4.
 

my supervisor want mi to save 10 sample of 10bit dds data in the addr.....
so i need to configure my ram core to be 100 bit wide??
 

Uh-oh. It sounds like you are unfamiliar with how RAM works. FPGA design requires a basic understanding of digital hardware design. Try a good introductory book such as "Digital Design" by Mano. (I don't know any "great" intro books.)

My Verilog example stores up to 1024 DDS samples in the RAM. The RAM is 12 bits wide by 1024 words deep.
 

oh...u mean.....1024 10bits sample issit?

or 1024/10 = 102.4 sample?

sorrie..i realli newbie...hahs
 

My example stores 1024 12-bit samples. That's 12288 bits total. Coregen lets you configure whatever size RAM you need.

The Virtex-4 contains many dual-port block RAMs. Each one stores up to 18432 bits.
 

what does "Block" means in dual port ram?? everytime i change the width setting...i notice the block value will also change....

for example

(page1)width = 16.......(page4)block used =1
(page1)width = 256.......(page4)block used =15
 

A "block" is one individual component, like one cube from a set of building block toys.

Your particular Virtex-4 contains some number of block RAMs. If your design needs more, you'll need a larger FPGA.

For more info on block RAMs, refer to your Virtex-4 User Guide.
 

if i use DinA......then i can only store my data in AddrA??

coz my supervisor wan mi to use Port A for Write and Port B for Read....issit possible?

how could it store data in AddrA...and read the same data in AddrB??
 

Remember this is a dual-port RAM. It provides two ports for simultaneously accessing the memory array.
It's fully described in the "Block RAM" chapter of the "Virtex-4 User Guide":
**broken link removed**

My Verilog example writes into port A, and reads from port B. I think that's what you need.
 

if in a Bram the PortB is unconnected and you want to write througth the port B data in an specific address how you do it? because with that simple verilog code you write not in a specific code..
 

Your question doesn't make sense. How can you use port B if it's unconnected?
 

the think is how to make the port B to be used to load the memory with data througth VHDL code.The portA is connected to the docm_cntlr and then in PowerPc. By making the PortB's signals as external in EDK and feed data from them nothing happend. so how you can make portB "alive"?
 

I've never debugged an EDK project, sorry!

I guess you should launch your simulator, or something like ChipScope, and try to see what's going wrong around the dual-port RAM.
 

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