What is the difference between Simulation and STA

Hello.
In one of my design , the STA tool indicate that it can run at 9ns clock cycle,after layout STA. But when running simulation, it suggest that the design can run at 10ns clock cycle.Why the result is different.Can somebody explain to me how STA work ? Thank in advance.

simulation : simulation is "dynamic timing analysis". meaning the test benches/ test vectors are used to sensitize each path and chk for the timing.
This is not the best way to verify the Timing , cos its not practically possible to sensitize each and every path in the design using test vectors !!

simulation is used to verify functionality of the design and not timing

STA : This instead of checking fir functionality, rather breaks up each and every path in the dsgn into timing arcs & verifies purely the timing between 2 sequential elements.

Hope this helps u in some way, if not wrt to the ex tht u have posted !!

WBR,
Lakshman

Dear
lakshman.ar is right. Simulation is just used for testing function of your design. But STA is one of step in design a chip.

Hi funzero,
STA tools are used for Timing sign off. By simulation tools , you cant say design can run at XXX frequency.

Lets how STA tools will work.

STA tools will divide the logic of the design into Timing Start points(SP) and Timing end points (EP). Valid SPs are Input port /FF clock pin and valid End points are FF Data pin and Output ports. After applying the clocks and your constraints, STA tools will try to check the timing path (Path is from Valid SP to Valid EP). Assume your design is single clock and it runs at 111Mhz(9ns). Tool will try to check every path will work at 111mhz or not. It wont check beyond that(Becasuee you constraint say check only for 111Mhz). Even though one path works at 150Mhz, it doesnt mean, your design can run at 150mhz.

Hope you got it..

Regards,
Sam

HI Funzero,

can you post the logfile hear such that we can look into that and design what is the problem.

Regards,
Ramesh.S