tcfk2
Newbie level 5
Hi everyone
I am designing a wideband single-ended LNA between 6GHz to 10GHz in 90nm CMOS. I adopted a inductively degenerated LNA with wide band match at the input.
I am puzzled by the allocations of the ground pins for this design. Nominally I have two ground pins for this design: one used for generating the bias network for this LNA and the other is the attenna ground. The substrate is connected to the bias ground, not the attenna ground.
I did so because I thought the attenna ground should be quite. Also I want to reduce the amount of substrate noise getting into the LNA's attenna ground. Therefore I used the bias ground for the substrate of the LNA. I also use multiple down-bonded for the bias ground to reduce its inductance to reduce substrate noise.
Is this a common way of doing this type of LNA design?
Feedbacks are most welcomed and appreciated!
Thank you very much.
Tony
I am designing a wideband single-ended LNA between 6GHz to 10GHz in 90nm CMOS. I adopted a inductively degenerated LNA with wide band match at the input.
I am puzzled by the allocations of the ground pins for this design. Nominally I have two ground pins for this design: one used for generating the bias network for this LNA and the other is the attenna ground. The substrate is connected to the bias ground, not the attenna ground.
I did so because I thought the attenna ground should be quite. Also I want to reduce the amount of substrate noise getting into the LNA's attenna ground. Therefore I used the bias ground for the substrate of the LNA. I also use multiple down-bonded for the bias ground to reduce its inductance to reduce substrate noise.
Is this a common way of doing this type of LNA design?
Feedbacks are most welcomed and appreciated!
Thank you very much.
Tony
