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Cascaded Integrator-Comb (CIC): a cascaded integrator-comb (CIC) is an efficient implementation of an interpolator (which increases the sample rate of a signal) or decimator (which decreases the sample rate), typically used in FPGA architectures. Contrary to the name, a CIC filter is a combination of a linear filter and an upsampler or downsampler.
A CIC filter consists of one or more integrator and comb filter pairs. In the case of a decimating CIC, the input signal is fed through one or more cascaded integrators, then a down-sampler, followed by one or more comb sections (equal in number to the number of integrators). An interpolating CIC is simply the reverse of this architecture, with the down-sampler replaced with a zero-stuffer (up-sampler).
Root-Raised Cosine (RRC): A symmetric discrete-time square-root-raised-cosine filter may be utilized to process a serial input signal and to produce an output square in each clock cycle. The filter may be adapted to decrease the computational complexity of the resulting calculations, making the filter amenable to use in power sensitive applications and in those situations where the available processor's performance is relatively limited.
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