USB H0st c0ntr0ller design with VHDL code

dear all

got the example code for the design, Tk a look ...
let us discuss how to implement to the FPGA

do we need controller inside? Like "NIOS"?
how to implement into the Altela Cyclone FPGA?

what is the difference between host controller and device controller?

USB is a token based bus. The host is the master while device is slave. All the transaction is initiated by host. The device need to respond to control/data/etc packets from host.

The code is well written. But it has too less coment. It takes time to understand the concepts behind the code. Not sure any more experienced guy can share more understandings on it.

Hi,

Is this behavioural or synthesizable code?
I don't know a lot about USB but the 'behavioural' line in the header tells me that is a model for simulation.

Any comments,

-maestor

The code seems synthesizable. The 'behavioral' just mean the way it designs the controller. Behavioral doesn't mean unsynthesizable.

Hi all.
Sorry, but this is most likely a device core. You can tell from line 74 of pdiusb.vhd:

"Reset from host detect"

A host would never need to detect a reset condition on the bus since only the host can assert a bus reset. Also, the design is a bit simplistic for a host controller. Many basic things are not present such as SOF generation, suspend/resume, etc...

Although the USB device is an easy thing to design, the host is quite difficult. USB is funny because they made it so asymmetric. All the difficulty was pushed to the host since it was assumed it would be on a PC and have unlimited resources. The device was made simple because it was predicted (correctly) that most products would end up being USB devices that attach to PCs.
strut911