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Minimum offset voltage with 0.18um CMOS process

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Ipanema

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Guys,

May I know what is the minimum achievable input offset voltage for comparator in 0.18um CMOS process? I can only achieve +/-6mV with a PMOS input differential pair simulated over process & mismatch in Monte Carlo analysis.

Does the second stage of comparator play a role in the offset voltage performance?

Thanks.
 

The offset voltage is dependant on your design. Small Vdsat of the input transistor will help you to reduce the offset voltage. The sechond stage offset should be divided by the gain of the first staage when it refers to the input
 

Does the second stage contribute to the input offset voltage? From MC simulation, the second stage does not contribute to input offset voltage. May I know why is it so?

Thanks.
 

symet offset by circuit design keep the same Vds

but random offset by Layout .. in gernel
tsmc umc have offset data

like x / [ ( W*L) ^0.5 ]
Mos W/L will have offset

you can see some LCD driver .. this circuit need many low offset OPA
 

Ipanema said:
Does the second stage contribute to the input offset voltage? From MC simulation, the second stage does not contribute to input offset voltage. May I know why is it so?

Thanks.
Click to expand...
The second contribute to the input offset. It needs to be divided by the gain of the first stage. Mabye the gain of your first stage is large.
 

we often talk about input-referred offset. So, if the gain of first stage is 1000, and second stage offset is 20mV for example, then input-referred offset is only 20mV/1000=0.02mV, very small. That's why second stage contribute lillte offset unless the gain of first stage is very small, which is not reasonable
 

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