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PLL testing issue with control voltage of VCO

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danda821

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I designed a PLL in CMOS and now is doing the testing. It is weird whenever I turn on the reference clock, the control voltage of VCO goes to VDD (1.2V) immediately. This happens even when the charge pump current is zero. I do not know what is going on.
 

Re: PLL testing question

danda821 said:
I designed a PLL in CMOS and now is doing the testing. It is weird whenever I turn on the reference clock, the control voltage of VCO goes to VDD (1.2V) immediately. This happens even when the charge pump current is zero. I do not know what is going on.


hi

could you draw your ckt in briefly,
can you see the oscillation?
is there any initiate-circuit to the control voltage node? maybe, this ckt has problem?

good luck.
jeff
 

Re: PLL testing question

Thanks.
This is a 5GHz PLL. There are PFD, charge pump, divider and VCO. The divider is multi-mode (eight), so it can be used to select different channel. The following shows the detail. I did not use any circuit to initialize the control voltage.
 

PLL testing question

It maybe the UP and Down signal to Charge Pump is cross inverse connected. You can check it.
and if not, I suggest that you should check each block separately.

Ryan
 

PLL testing question

But vctrl goes to high even when charge pump current is zero.
 

PLL testing question

I wonder how to set the charge pump current to zero? Maybe the leakage current are exist or some other effects make the vctrl goes to high.
I suggest that check the output of charge pump, and find out how does the vctrl go to high. then check when vctrl is high, whether can VCO oscillate.

Ryan
 

PLL testing question

Did the VCO oscillate
 

PLL testing question

Can be stable in close-loop ?
 

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