rinaishlene
Junior Member level 3
I will be using VHDL\Verilog Code to simulate the function the datapath proposed in this paper
"A New hardware Realization of Digital Filter"
By ABRAHAM PELED and BEDE LIU
IEEE Transaction on Acoustics,Speech and Signal Processing,DEC 1974
Here I attached the diagram of the datapath
My question is
1)Is it appropriate to use two 2-bit SIPO shift register to represent (SR1 and SR2) and (SR3 and SR4)?
2)The output of the shift register will be the address of the ROM but then each bit of address of the ROM will be multiplied with the each coefficient filter (a0 to b1) given to create the function phi(the output of the ROM).Where should the function phi take place?Is it inside the ROM?
Appreciate any help.
Thank you
"A New hardware Realization of Digital Filter"
By ABRAHAM PELED and BEDE LIU
IEEE Transaction on Acoustics,Speech and Signal Processing,DEC 1974
Here I attached the diagram of the datapath
My question is
1)Is it appropriate to use two 2-bit SIPO shift register to represent (SR1 and SR2) and (SR3 and SR4)?
2)The output of the shift register will be the address of the ROM but then each bit of address of the ROM will be multiplied with the each coefficient filter (a0 to b1) given to create the function phi(the output of the ROM).Where should the function phi take place?Is it inside the ROM?
Appreciate any help.
Thank you