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How to simulate the offset voltage of the comparator??

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leg1234

leg1234

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Hi, all

I am designing a latched comparator (dynamic type).
How can I set up the simulation to get the performance in offset and speed??
I also need Monte Carlo and Corner model verification. Thank you.

leg1234
 

i also need this help

look forward to your help
 

I think the Vos of the comparator will not appear correctly until you draw the layout and finish the post-simulation.
 

use Monte Carlo analysis need some variation parameter of your mosfet or resistor, for example tox, delta_L, delta_W and delta Vth
 

Humungus said:
See my answer in post
Click to expand...

Is this the same procedure even for folded cascoded Opamp structure ?
 

kumar123,

The procedure I describe is for clocked (latched) comparator. In case of continuous time comparator, you need only perform a sweep of your input keeping the other one to a reference and then find the level at which your output toggle through a .DC analysis (this avoids errors due to the switching delay).
 

Humungus said:
kumar123,

The procedure I describe is for clocked (latched) comparator. In case of continuous time comparator, you need only perform a sweep of your input keeping the other one to a reference and then find the level at which your output toggle through a .DC analysis (this avoids errors due to the switching delay).
Click to expand...

Meaning as listed in Textbooks is it necessary to use dual power supply (Vdd=1.8 Vss=-1.8) and check the Vos for 0 Axis crossing of Sweep (say input) ?
 

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