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Question on At-speed test for DFT

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question:
Can I set two parts of scan chain? one is basic scan chain path ,
the others is a scan chain with clock controller for At-speed testing ?


With DFT compiler-TetraMax flow or any tools ?
 

Hi,

I am unable to understand what u r asking can u explain a bit clearly.
in the at-speed testing the clock will be muxed with sliced pll clock at the intial stage.so the clock tree is same for both ordenary and at-speed clock but the at the time of atspeed we will select the pll clock instred of shift clock.

Regards,
Ramesh.S
 

Dude,

At-speed is one of the technique to test the defects in a design.

Timing failure occurs when a circuit opeaayes corectly at a slow clock rate, and then fails when made to run at the normal system speed.

dealy variations exist in the chip, results in partial conducting transistors, and resistive bridges.

At-Speed is used t run to solve this problem.

Scan chain is another way, which can be full scan or partial scan . but partial scan is done since timing is less

Both can be done.


Hope i have answered

Phutane

phutane
 

You should know does the ATE can support you DFT pattern, usally ATE just one clock .
 

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