FPGA to ASIC? I think i am missing some knowledge here?

OK i am a senior about to get my BS in EE after 4-5 more classes, but i feel there are many things i still do not know or understand and this is one of them.

I have taken all the undergrad digital classes we offer in our department (Digital Logic(learn about gates) , Microprocessor Apps( hardware/software interfacing), Digital Design (VHDL using FPGA), and Computer Architecture ( use VHDL/Verilog to design a MIPS32 CPU). I have learn a lot about implementing digital circuit in reprogrammable devices such as FPGAs and CPLD but what i do not understand if what if i wanted to get a ASIC design of my circuit?

Is there software like the software i use for FPGA design, Quartus, that takes logic gates and HDL and makes a simplistic layout of transistors ready to be sent to a FAB? Or does every ASIC have to be designed from transistor to transistor? I have not taken a class yet with the CMOS transistor designing, in one more week i will start it, Digital Integrated Circuits, as i am sure this will clear up some confusing. But till then what steps from start to finsih do companies take to go from logic gates to HDL to actual ASIC IC chips?

Thank and looking forward to the response,
Chris

Basically you wanted to know asic flow, following site will give a good description about this.

https://vlsichipdesign.com/vlsidesignflow.html

Hope this will help.

Hi,
1. Dont worry about not knowing too much. I believe that Unis now lag more than ever to the industry in teaching VLSI design. You will only learn it when you join industry. No one from uni has enough knowledge these days(unless you are a PhD student)
2. As far as ASIC for your circuit is concerned, Well to design an ASIC, we do use HDL to code the circuit as you would to for an FPGA, but from here ASIC design takes a new direction. Once you have HDL, you 'synthesize' it into gates. These are logic gates from a library of gates belonging to a FAB. The process of converting HDL into connection of 'gates' is also called 'mapping to technology library' or formally synthesis. This gate level descripton is called 'netlist'. Then you have tools like 'Magma' or 'First Encounter' which takes the 'netlist' as input, and some other things like 'constraints' floor plan etc.. as inputs and then 'place and route' your nelitst into its physcial view called layout. Once layout passes its verification checks, its 'taped out' and sent to FAB for fabrication.
Well that sounds very easy but in fact its a very complicated process.
Kr,
Avi
http://www.vlsiip.com

Thank you, your comments and the link was very helpful and It makes sense.

Thanks,
Chris