Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Problem on dracula lvs layout extraction

Status
Not open for further replies.
Y

yann_sun

Member level 1
Joined
Jul 17, 2006
Messages
38
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,286
Activity points
1,529
Hi,all
How does dracual LVS extract channel width and length of MOS in layout?
I mean how the "W=** L=**" expression is obtained by dracula lvs run. This expression is locating on the right side(layout devices, nodes and parameters) of .lvs file? and, if i want to change the formula for calculating the value of W or L, even those of AS/AD/PS/PD for lpe, what should i do?
It is always easy for calibre lvs users to find the expression and revise.

Thanks in advance
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top