Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Types of Verifications ?

Status
Not open for further replies.

truebs

Full Member level 5
Joined
Jan 21, 2005
Messages
310
Helped
22
Reputation
44
Reaction score
4
Trophy points
1,298
Location
Asia
Activity points
2,980
Hi,

Can some one please share your views on following terms :-

1) Formal Verification
2) Functional Verification

with respect to ASIC flow, i.e. what are these and when and where do we perform these verifications ?

How do we do these ? What tools are generally used ? Synopsys ?

Thanks,
truebs
 

truebs said:
Hi,

Can some one please share your views on following terms :-

1) Formal Verification
2) Functional Verification

with respect to ASIC flow, i.e. what are these and when and where do we perform these verifications ?

How do we do these ? What tools are generally used ? Synopsys ?

Thanks,
truebs

Functional Verification is usually done in 2 major means: Dynamic and Static. Dynamic - simulation based. Static - lint, formal methods. Tools - do a google search or visit EDA vendors' pages, you will see. Also deepchip.com has the tool list.

BTW - we elaborate in great detail each of these terminoligies, approaches with real life tools such as VCS, Modelsim, Leda etc. in our Verification trainings such as CFV. See: www.noveldv.com and drop us an email at cvc.training <> gmail.com if interested.

Cheers
Ajeetha, CVC
www.noveldv.com
 

Functional verification is done when we have our DUT RTL is ready and we here check for all the functionality of our design (for which it is designed). Basically we test functionality of design by some HVL language (like verilig, vhdl, specman, vera, system verilog and so on).

In Formal Verification we check intended design functionality has not been changed during any time in different stage of ASIC flow. As for example when we synthesize our RTL into netlist, we use formal verificatio to see if synthesis tool has not changed any functionlity (so we do formal verification between golden RTL and netlist) similarly we can perform formal verification on prelayout and post layout netlist to see nothing has been changed. For formal verification we generally use Cadence Conformal , Synopsis Formality.

Hope this helps.

Regards,
pintuinvlsi
 

    truebs

    Points: 2
    Helpful Answer Positive Rating
Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top