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PLL Design Frequency/Phase locking

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rsobin

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I am working on designing a PLL system where the VCO output is sent through a sensor and is then brought back into the PFD. When the VCO output goes through the sensor a phase delay related to the resonance of the sensor is created. I was wondering about incorporating a phase delay in the feedback loop(not the sensor loop) in order to get the PLL to lock on to a certain frequency corresponding with a specific phase delay created by the sensor. Im not sure if this is a realistic idea but think it might be and if so need some ideas on simple phase delay circuits.

I have a working pll based on an xor gate and integrator but you have to help the circuit lock and the circuit sometimes looses lock.

Thanks
 

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