bitblue
Newbie level 3
Hi friends, I'v got two questions to ask.
--1--
If the circuit need more than 10 commands to operate, and I wanna design a fsm to realize this function. The question is considering some other inputs, then fsm' s decoding combinational logic will be complicated slowing down the operating frequency? how can I optimize the circuits to improve the circuit speed. the key things we should do is to diminize the combinational delay, how? who can give an example explaining the fsm partition can solve this problem.
--2--
the other question is related the critical signal. In the n level combinational logic design, we can put this critical signal in the last level to solve this problem. And in the state machine, this critical signal also can be seperated from other signal to solve this problem. But the question is before you design the circuit, how to judge which is critical signal which is not. I judge the critical signal after timing analysis, but at that time the circuit has been designed and the next step is to redesign it according the timing analysis. How to judge whether this signal is critical or not ? some people may say it is the signal coming later or need more time to propagate.
but how to judge the later before you design the circuit.
Best Regards
bitbue
--1--
If the circuit need more than 10 commands to operate, and I wanna design a fsm to realize this function. The question is considering some other inputs, then fsm' s decoding combinational logic will be complicated slowing down the operating frequency? how can I optimize the circuits to improve the circuit speed. the key things we should do is to diminize the combinational delay, how? who can give an example explaining the fsm partition can solve this problem.
--2--
the other question is related the critical signal. In the n level combinational logic design, we can put this critical signal in the last level to solve this problem. And in the state machine, this critical signal also can be seperated from other signal to solve this problem. But the question is before you design the circuit, how to judge which is critical signal which is not. I judge the critical signal after timing analysis, but at that time the circuit has been designed and the next step is to redesign it according the timing analysis. How to judge whether this signal is critical or not ? some people may say it is the signal coming later or need more time to propagate.
but how to judge the later before you design the circuit.
Best Regards
bitbue