Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

How can we check Phase margin of my PLL..

Status
Not open for further replies.
S

savithru

Member level 1
Joined
Aug 18, 2005
Messages
36
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,286
Activity points
1,628
Hi,

I want to know how I can check the Phase margin of my PLL. I am using the specterRF.

Also is it possible to check/plot the loop gain.

Kindly reply.

Thanks & Regards
SavithRu
 

u need a small signal model by matlab or verilogA
 

safwatonline said:
u need a small signal model by matlab or verilogA
Click to expand...

hi, safwatonline

Thank you very much for replying...

"small signal model" meanse the behaviaral model? or some thing else.

Cant we do it directly in spectre?

Pls reply.
 

yes ,it means behaviour model in the phase domain,
well to calculate the PM u need some open loop so u must use small signal model
 

I will reply how to do in spectre.

First, you need to model PFD+CP. You can use VCCS source.
The gain of PFD+CP is Icp/2/pi

Second the VCO is modeled by Kvco/S. You can use a capacitor to model them.

Third, you can model divider. It is only a gain with 1/N

Fourth, you can model the loop filter using real R and C.

Then, you can connect them in an open-loop mode and apply frequency sweep.

You can get what you want.

If you connect them in a closed loop mode, you can know the overshoot when you apply a step input.

Yibin.
 

    S

    savithru

    Points: 2
    Helpful Answer Positive Rating
Hallo, try it also. GBr
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top