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bandgap floor planning

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vishal.vernekar

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can any one tell me whats best floor plan for banndgap, where bjt,resistor ,amp should be placed..?

graphical box representation will be great help ....

thanks in advance

vishal
 

Considering the matching about the components, such as the bipolar ,the pata current 's resistors and the mos of the AMP. Then you should consider avoiding the noise from the digital parts.
 
Dear vishal.vernekar :


Please reference these Pics.


mpig
 

Does somebody have ideas why the bandgap circuit is not suggested to place close to the scribe line?
 

Nice layout! -where is the bandgap layout in this sample? or is it the whole bandgap layout?
 

The picture shows the two pnp(left down corner), MOSFET in the opamp. And it shows part of the resistor array(up right).
 

elantra said:
Does somebody have ideas why the bandgap circuit is not suggested to place close to the scribe line?
Click to expand...


why do you think so? where did you get this information?
 
thanks yzcom .......

it really helped me ....

can u do one more favor to us...

just highlight over picture amplifier ,resistor, sensitive nodes ,where shielding can be done .....

i mean layout constraint with explanation over picture....

it will help community lot ...

anyway thanks lot for actual picture ...... :)
 

Guys,

Can you show me how to do a good matching layout for current mirror with degeneration? The transistor and resistor ratio are 20:1. If this ratio is not good, may I know what is the "rule of thumb" to select an optimum ratio for best layout?

Thanks. :)
 

Anyone? Pls help. With these layout for 20:1 ratio, what would be the matching percentage from your experience?

Regards.

Added after 1 minutes:

Anyone? Pls help. With these layout for 20:1 ratio, what would be the matching percentage from your experience?

Regards.
 

I think in above picture shown 2 placement both are centroid matching. for percentage point of view squarish placement is good.
 

keep it conpact and match
 

the layout is compact and very nice
 

I think Layout 1 has better matching than layout 2......Layout 1 has centroid matching.
 

They tell you don't place it near the scribe line because stress at the edge of the chip is maximum.

Since thermal expansion of the IC is different than the leadframe, you can consider the chip bending very slightly. The exact center does not bend at all because the forces on either side are equal. The four sides bend more. So it places unequal stress on the sides of your your delta-Vbe and you get offset.

But really, as long as you don't place it in the corner it's fine. At the top scribe, dead center has worked for me many times. But I trim my reference so small random offsets don't really matter to me.
 

Thanks, electronrancher!

You know, many experienced designer told me about this issue, but I did't have chance to know why.

thanks again.
 

The another problem which gets on the surface becasue of stree is
the change of the bandgap of silicon itself due to the variation in
interatomic spacing due to the stree. This phenomenon called as Package Shift
effect, as the stress is a function of the packaging.

Regards
Raduga
 

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