Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
PT, as far as i know, can't fix the timing violations. but, hold violations are fixed using buffers in the P&R stage, or by adding an additional flop(making sure functionality is met) in the RTL stage.
For setup violation, either better constraints or methods such as inserting buffers in the nets or useful skew are used in the backend stage.
If more methods are there, or if i've made mistakes somewhere, please let me know.
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
