sujithchakra
Junior Member level 1
verilog array slice
Could any one please help me..... whats wrong in the following statements?
reg [7:0] a [0:7];
a[1][0]<=1'b1; // I GET "SYNTAX ERROR" here when I try to assign "1" to
element indexed [1][0] .I am using Cadence Verilog - XL to compile the code.
I find the syntax right.Could anyone please correct me if I am wrong?
Thank you
Could any one please help me..... whats wrong in the following statements?
reg [7:0] a [0:7];
a[1][0]<=1'b1; // I GET "SYNTAX ERROR" here when I try to assign "1" to
element indexed [1][0] .I am using Cadence Verilog - XL to compile the code.
I find the syntax right.Could anyone please correct me if I am wrong?
Thank you