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hold requirement on flip flops

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mikkie_r

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Hey

What exactly is a hold requirement? I'm not referring to the definition of the minimu, time a signal has to stay stable after clock rise.

I want to know why is there a hold requirement? What will happen to the elements inside the flip flop (the transistors) if I change the data too quickly? In setup I need to get the signal soon to load the input capacitor. But in hold the capacitor is already loaded - so why do I need to hold the signal stable?

Thanks
Mikkie
 

Hold requirement results from the master-slave architecture of the flip flops.
You can study the condition when two flip flops are conected directly.
 

If you analyze the master slave architecture you'll find that on the rising edge of the clock (for positive edge trigerred the master master latch works on negative level) the data is transferring from master to slave .Due to RC delay it takes some amount of time (i.e. the hold time) for that. As far as your question is concerned that node is already charged then you'll better understand this concept when search on google for tutorials related to charge sharing. This node can share charge to output node but does not charge it to full level..(some source should be there)..
 

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