chemaphy
Junior Member level 2
Hi Everyone,
I have just designed a 8-bit folding interpolation ADC. When I simulate my ADC, I cannot get to 8-bit of resolution. The SNR that I got from the power spectrum is only -30dB. The noise level is at -40dB. Is there any technique I can use to lower the noise level in the ADC. Can anyone who has experience with folding interpolation ADC let me know which part in the ADC contribute such a high noise?
Thanks,
chemaphy
I have just designed a 8-bit folding interpolation ADC. When I simulate my ADC, I cannot get to 8-bit of resolution. The SNR that I got from the power spectrum is only -30dB. The noise level is at -40dB. Is there any technique I can use to lower the noise level in the ADC. Can anyone who has experience with folding interpolation ADC let me know which part in the ADC contribute such a high noise?
Thanks,
chemaphy